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Embedian, Inc.

27

SMARC-FiMX6 Computer on Module User’s Manual v.1.2

Freescale i.MX6 CPU

SMARC-FiMX6 Edge

Golden Finger

Net

Names

(Carrier

Board)

Color

24-bit
Color

Map

Ball

Mode

Pin Name

Pin#

Pin Name

W24

ALT0

DISP0_DAT23__

IPU1_DISP0_DATA23

S118

LCD_D23

(MSB)

LCD_D23

RED

R7

V24

ALT0

DISP0_DAT22__

IPU1_DISP0_DATA22

S117

LCD_D22

LCD_D22

R6

T20

ALT0

DISP0_DAT21__

IPU1_DISP0_DATA21

S116

LCD_D21

LCD_D21

R5

U22

ALT0

DISP0_DAT20__

IPU1_DISP0_DATA20

S115

LCD_D20

LCD_D20

R4

U23

ALT0

DISP0_DAT19__

IPU1_DISP0_DATA19

S114

LCD_D19

LCD_D19

R3

V25

ALT0

DISP0_DAT18__

IPU1_DISP0_DATA18

S113

LCD_D18

LCD_D18

R2

U24

ALT0

DISP0_DAT17__

IPU1_DISP0_DATA17

S112

LCD_D17

LCD_D17

R1

T21

ALT0

DISP0_DAT16__

IPU1_DISP0_DATA16

S111

LCD_D16

(LSB)

LCD_D16

R0

T22

ALT0

DISP0_DAT15__

IPU1_DISP0_DATA15

S109

LCD_D15

(MSB)

LCD_D15

GREEN

G7

U25

ALT0

DISP0_DAT14__

IPU1_DISP0_DATA14

S108

LCD_D14

LCD_D14

G6

R20

ALT0

DISP0_DAT13__

IPU1_DISP0_DATA13

S107

LCD_D13

LCD_D13

G5

T24

ALT0

DISP0_DAT12__

IPU1_DISP0_DATA12

S106

LCD_D12

LCD_D12

G4

T23

ALT0

DISP0_DAT11__

IPU1_DISP0_DATA11

S105

LCD_D11

LCD_D11

G3

R21

ALT0

DISP0_DAT10__

IPU1_DISP0_DATA10

S104

LCD_D10

LCD_D10

G2

T25

ALT0

DISP0_DAT9__

IPU1_DISP0_DATA09

S103

LCD_D9

LCD_D9

G1

R22

ALT0

DISP0_DAT8__

IPU1_DISP0_DATA08

S102

LCD_D8

(LSB)

LCD_D8

G0

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Summary of Contents for SMARC-FiMX6

Page 1: ...s Manual v 1 2 SMARC Computer on Module Freescale i MX6 Cortex A9 24bits Parallel LCD LVDS HDMI 4 x COM Ports 2 x SDHC 1 x USB Host 2 0 1 x USB OTG 1 x 10 100 1000M Gigabit Ethernet 2 x CAN Bus 2 x SP...

Page 2: ...Embedian Inc 2 SMARC FiMX6 Computer on Module User s Manual v 1 2...

Page 3: ...uter on Module User s Manual v 1 2 Revision History Revision Date Changes from Previous Revision 1 0 2014 11 20 Initial Release 1 2 2015 2 25 Documentation Wording Fixed and add section 2 1 8 and add...

Page 4: ...owing lists the trademarks of components used in this board ARM is a registered trademark of ARM Limited Android is a registered trademark of Google Linux is a registered trademark of Linus Torvalds W...

Page 5: ...cians and engineers from EMBEDIAN and or its subsidiaries and official distributors are available for technical support We are committed to making our product easy to use and will help you use our pro...

Page 6: ...C FIMX6 GENERAL FUNCTIONS 18 2 2 SMARC FIMX6 DEBUG 94 2 3 MECHANICAL SPECIFICATIONS 94 2 4 ELECTRICAL SPECIFICATIONS 109 2 5 ENVIRONMENTAL SPECIFICATIONS 114 CHAPTER 3 CONNECTOR PINOUT 116 3 1 SMARC F...

Page 7: ...names pathnames and code examples Embedian Information Document Updates Please always check the product specific section on the Embedian support website at www embedian com for the most current revisi...

Page 8: ...Embedian Inc 8 SMARC FiMX6 Computer on Module User s Manual v 1 2 manual and related documentation for additional information...

Page 9: ...r s Manual v 1 2 Introduction This Chapter gives background information on the SMARC FiMX6 Section include Features and Functionality Module Variant Block diagram Software Support Hardware Abstraction...

Page 10: ...interfaces in a cost effective low power miniature package Embedian s SMARC FiMX6 thin and robust design makes it an ideal building block for reliable system design The module is the ideal choice for...

Page 11: ...board name serial number and revision information Additional Interface 4 x UARTs 2 x SPI 4 x I2C 1 x I2S 2 x CAN Bus 1 x PWM 12 x GPIOs 1 x SATA Dual and Quad only WDT SW Support L inux Yocto Ubuntu...

Page 12: ...U dual lite core running up to 1GHz D dual core running up to 1GHz Q quad core running up to 1GHz 2 1G 1GB DDR3 memory 2G 2GB DDR3 memory only for dual and quad core 3 P if 1 8V VDDIO Leave it Blank i...

Page 13: ...1 3 Block Diagram The following diagram illustrates the system organization of the SMARC FiMX6 Arrows indicate direction of control and not necessarily signal flow Figure 1 SMARC FiMX6 Block Diagram D...

Page 14: ...eMMC electrical standard is defined by JEDEC JESD84 B45 and the mechanical standard by JESD84 C44 www jedec org The I2C Specification Version 2 1 January 2000 Philips Semiconductor now NXP www nxp com...

Page 15: ...not usually available outside of Embedian without special permission The other schematics will be available Contact your Embedian representative for more information The SMARC Evaluation Carrier Boar...

Page 16: ...iles and Linux BSP Documentation Oct 29 2014 Rev L3 10 17 IMX6_JB43_110_ANDROID_SOURCE_BSP i MX 6Quad i MX 6Dual i MX 6DualLite i MX 6Solo and i MX 6Sololite Android jb4 3_1 1 0 0 BSP Documentation an...

Page 17: ...on Module User s Manual v 1 2 Specifications This Chapter provides SMARC FiMX6 specifications Section include SMARC FiMX6 General Functions SMARC FiMX6 Debug Mechanical Specifications Electrical Spec...

Page 18: ...ARC FiMX6 Feature Support Instances LVDS Display Support 1 Yes 1 18 or 24 bits Note1 Parallel LCD Support 1 Yes 1 24 bits HDMI Display Support 1 Yes 1 CSI Camera Support Dual and Quad lanes 2 Yes 1 Qu...

Page 19: ...2 I O Voltage 1 8V Level Support Yes I O Voltage 3 3V Level Support Yes Note 1 Single channel LVDS interface 1 x 18 bpp OR 1 x 24 bpp up to 85 MHz per interface e g 1366x768 60Hz 35 blanking 2 Dual ch...

Page 20: ...6x768 60Hz 35 blanking Dual channel LVDS interface 2 x 18 bpp OR 2 x 24 bpp up to 170 MHz pixel clock e g 1600x1200 60 Hz 35 blanking Single channel LVDS interface 1 x 18 bpp or 1 x 24 bpp up to 85 MH...

Page 21: ...e to use the LVDS interface as two independent single LVDS channels To do this it is recommended to configure the LVDS display in the bootloader Three independent displays are possible when connected...

Page 22: ...res Quad 4 Cores 2D Core Vivante GC320 2D Performance 633M pixels sec raw performance Vector Graphics Core Vivante GC355 API DirectX OpenGL OpenGL ES 1 1 2 0 3 0 OpenCL 1 1 EP OpenVG 1 1 Hardware Acce...

Page 23: ...d SPI NOR flash first The firmware in NOR flash will read the configuration from the boot selection and boot up the devices from that selected 2 1 7 Clocks A 32 768 KHz clock is required for the i MX6...

Page 24: ...terfaces is the maximum clock of the LVDS serializer For single channel output the pixel clock is limited to 85 MHz per LVDS port This results in a maximum resolution of WXGA 1366x768 60HZ with 35 bla...

Page 25: ...tage swing may be used directly with 3 3V capable Carrier Board LVDS transmitters such as the TI SN75LVDS83B The 3 3V signaling is suitable for direct connection to a parallel flat panel in most cases...

Page 26: ...s used for a 24 bit color implementation come out on Freescale i MX6 DISP0_DAT 17 16 DISP0_DAT 9 8 and DISP0_DAT 1 0 Since 18 bit configuration and 24 bit configuration use the same MSB signals we can...

Page 27: ...3 V25 ALT0 DISP0_DAT18__ IPU1_DISP0_DATA18 S113 LCD_D18 LCD_D18 R2 U24 ALT0 DISP0_DAT17__ IPU1_DISP0_DATA17 S112 LCD_D17 LCD_D17 R1 T21 ALT0 DISP0_DAT16__ IPU1_DISP0_DATA16 S111 LCD_D16 LSB LCD_D16 R0...

Page 28: ...MSB LCD_D7 BLUE B7 R23 ALT0 DISP0_DAT6__ IPU1_DISP0_DATA06 S99 LCD_D6 LCD_D6 B6 R25 ALT0 DISP0_DAT5__ IPU1_DISP0_DATA05 S98 LCD_D5 LCD_D5 B5 P20 ALT0 DISP0_DAT4__ IPU1_DISP0_DATA04 S97 LCD_D4 LCD_D4 B...

Page 29: ...HS N20 ALT0 DI0_PIN3__ IPU1_DI0_PIN03 S121 LCD_VS LCD_VS T5 ALT5 GPIO_0__ GPIO1_IO00 S127 LCD_BKLT_EN LCD_BKLT _EN T1 ALT5 GPIO_2__ GPIO1_IO02 S133 LCD_VDD_EN LCD_VDD_ EN T4 ALT5 GPIO_1__ PWM2_OUT S14...

Page 30: ...tions leave the two LS bits D8 D9 not connected LCD_D 0 7 Output CMOS VDD_IO 8 bit BLU color data 18 bit display implementations leave the two LS bits D0 D1 not connected LCD_PCK Output CMOS VDD_IO Pi...

Page 31: ...m the same i MX6 source Edge Golden Finder Signal Name Direction Type Tolerance Description LCD_VDD_EN Output CMOS VDD_IO High enables panel VDD LCD_BKLT_EN Output CMOS VDD_IO High enables panel backl...

Page 32: ...maximum data rates The data rates supported are as follows For single channel output Up to 85 MHz per interface e g 1366x768 60 Hz 35 blanking For dual channel output Up to 170 MHz pixel clock e g 160...

Page 33: ...Embedian Inc 33 SMARC FiMX6 Computer on Module User s Manual v 1 2 The following figure shows the LVDS LCD block diagram Figure 3 SMARC FiMX6 LVDS LCD Diagram...

Page 34: ...4 W2 ALT0 LVDS0_TX3_N S138 LVDS3 LVDS0_D3 V3 ALT0 LVDS0_CLK_P S134 LVDS_CK LVDS0_CK LVDS0 LCD differential clock pairs V4 ALT0 LVDS0_CLK_N S135 LVDS_CK LVDS0_CK LVDS Channel 1 Y2 ALT0 LVDS1_TX0_P S62...

Page 35: ...Interface HDMI is a licensable compact audio video connector interface for transmitting uncompressed digital streams HDMI encodes the video data into TMDS for digital transmission and is backward com...

Page 36: ...Embedian Inc 36 SMARC FiMX6 Computer on Module User s Manual v 1 2 The following figure shows the HDMI block diagram Figure 4 SMARC FiMX6 HDMI Diagram...

Page 37: ..._D1 HDMI_D1 K3 N A HDMI_D2M P93 HDMI_D2 HDMI_D2 TMDS HDMI data differential pair 2 K4 N A HDMI_D2P P92 HDMI_D2 HDMI_D2 J5 N A HDMI_CLKM P102 HDMI_CK HDMI_CK HDMI differential clock output pair J6 N A...

Page 38: ...VDD_IO I2C data line dedicated to HDMI HDMI_CTRL_CK Bi Dir OD CMOS VDD_IO I2C clock line dedicated to HDMI HDMI_CEC Bi Dir CMOS VDD_IO HDMI Consumer Electronics Control 1 wire peripheral control inter...

Page 39: ...USB 0 1 Per the SMARC specification the module supports a USB On The Go OTG port capable of functioning either as a client or host device on the SMARC USB0 port The SMARC FiMX6 module also supports o...

Page 40: ...D0__ GPIO1_IO30 ENET_TXD1__ GPIO1_IO29 P62 USB0_EN_OC USB0_EN_OC USB Port0 power enable over current indication signal E9 Turn on USB_OTG_VBUS P63 USB0_VBUS_DET USB0_VBUS_DET USB host power detection...

Page 41: ...Pulled low by Module OD driver to disable USB0 power Pulled low by Carrier OD driver to indicate over current situation A 10k pull up is present on the Module to a 3 3V rail The pull up rail may be sw...

Page 42: ...ule an OD driver on the Module and if the OC over current monitoring function is implemented on the Carrier an OD driver on the Carrier The use is as follows 1 On the Carrier board for external plug i...

Page 43: ...C condition will not last long as the USB power switch is disabled when the switch IC detects the OC condition 6 If the USB power to the port is disabled USBx_EN_OC is driven low by the Module then th...

Page 44: ...dication logic implementation is shown in the following block diagram There are 10k pull up resistors on the Module on the SMARC USBx_EN_OC lines Outputs driving the USBx_EN_OC lines are open drain Th...

Page 45: ...ust be active high and the Over Current pin OC must be open drain active low these are commonly available No pull up is required on the USB power switch Enable or OC line on carrier board they are tie...

Page 46: ...physical layer PHY transceiver with variable I O voltage that is compliant with the IEEE 802 3 2005 standards The AR8035 supports communication with an Ethernet MAC via a standard RGMII interface The...

Page 47: ...Embedian Inc 47 SMARC FiMX6 Computer on Module User s Manual v 1 2 This is diagrammed below Figure 7 Gigabit Ethernet Connection from i MX6 to Qualcomm Atheros AR8035...

Page 48: ...of the 4 data bits that are sent by the transceiver on the receive path B23 ALT1 RGMII_RD1__ RGMII_RD1 28 RXD1 RMII_RD1 Bit 1 of the 4 data bits that are sent by the transceiver on the receive path B2...

Page 49: ...he MAC transmits data to the transceiver using this signal F20 ALT1 RGMII_TD1__ RGMII_TD1 35 TXD1 RGMII_TD1 The MAC transmits data to the transceiver using this signal E21 ALT1 RGMII_TD2__ RGMII_TD2 3...

Page 50: ...al Transmit Receive Negative Channel 0 P28 GbE_CTREF GBE_CTREF Center tap reference voltage 12 TRXP1 P27 GbE_MDI1 GBE_MDI1 Differential Transmit Receive Positive Channel 1 13 TRXN1 P26 GbE_MDI1 GBE_MD...

Page 51: ...4 LED_10_100 P21 GbE_LINK100 GBE_LINK100 Link Speed Indication LED for 100Mbps Could be able to sink 24mA or more Carrier LED current 22 LED_1000 P22 GbE_LINK1000 GBE_LINK1000 Link Speed Indication LE...

Page 52: ...2 to magnetics Media Dependent Interface GBE_MDI3 GBE_MDI3 Bi Dir GBE_MDI Bi directional transmit receive pair 3 to magnetics Media Dependent Interface GBE_100 Output OD CMOS 3 3V Link Speed Indicatio...

Page 53: ...Configuration Halo HFJ11 1G02E Integrated RJ45 8 0o C 70o C HP Auto MDIX UDE RB1 BA6BT9WA Integrated RJ45 8 40o C 85o C HP Auto MDIX Halo TG1G S002NZRL 24 pin SOIC W 8 0o C 70o C HP Auto MDIX For ind...

Page 54: ...from the Freescale i MX6 processor to the PCI Express port A of the SMARC FiMX6 edge finger These signals support PCI Express Gen 2 0 interfaces at 5 Gb s and are backward compatible to Gen 1 1 inter...

Page 55: ...Port A clock request input D7 CLK1_P P83 PCIE_A_REFCK PCIE_A_REFCK Differential PCI Express Reference Clock Signals for Lanes A C7 CLK1_N P84 PCIE_A_REFCK PCIE_A_REFCK B2 PCIE_RXP P86 PCIE_A_RX PCIE_A...

Page 56: ...data pair 0 No coupling caps on Module PCIE_A_REFCK PCIE_A_REFCK Output LVDS PCIe Differential PCIe Link A reference clock output DC coupled PCIE_A_CKREQ Input CMOS 3 3V PCIe Port A clock request inp...

Page 57: ...o SMARC FiMX6 edge finger per defined in SMARC specification The SMARC FiMX6 offers this SATA port on the MXM connector This port supports SATA I 1 5Gbps and SATA II 3Gbps and is compliant with SATA s...

Page 58: ...Embedian Inc 58 SMARC FiMX6 Computer on Module User s Manual v 1 2 The following figure shows the SATA port A block diagram Figure 9 SATA Block Diagram...

Page 59: ...olden Finger Net Names Note Ball Mode Pin Name Pin Pin Name SATA B14 SATA_RXP P51 SATA_RX SATA_RX Receive Input differential pair A14 SATA_RXM P52 SATA_RX SATA_RX B12 SATA_TXM P49 SATA_TX SATA_TX Tran...

Page 60: ...ce Description SATA_TX SATA_TX Output SATA Differential SATA 0 transmit data Pair Series coupling caps is on the Module Caps is 0402 package 0 1uF SATA_RX SATA_RX Input SATA Differential SATA 0 transm...

Page 61: ...ted device The role of the camera ports is to receive input from video sources and to provide support for time sensitive signals to the camera Non time sensitive controls such as configuration reset a...

Page 62: ...Embedian Inc 62 SMARC FiMX6 Computer on Module User s Manual v 1 2 The following figure shows the serial camera interface block diagram Figure 10 MIPI Serial Camera Interface Block Diagram...

Page 63: ...era Interface A17 ALT4 NANDF_CS2__ CCM_CLKO2 S6 CAM_MCK CAM_MCK Master clock output for CSI camera support F4 CSI_CLK0M P4 CSI1_CK CSI1_CK CSI1 differential clock inputs F3 CSI_CLK0P P3 CSI1_CK CSI1_C...

Page 64: ...ence we leave this pin floating The CSI0 camera group is not used in SMARC FiMX6 PCAM_ON_CS0 is also floating on module 2 1 16 2 Camera I2C Support The I2C_CAM_ port is intended to support serial and...

Page 65: ...mera In CSI1 Edge Golden Finder Signal Name Direction Type Tolerance Description CSI1_D 0 3 CSI1_D 0 3 Input LVDS D PHY CSI1 differential data inputs CSI1_CK CSI1_CK Input LVDS D PHY CSI1 differential...

Page 66: ...two 4bit SDIO interface per the SMARC specification From the definition of SMARC specification one will be interfaced to SD SDHC card or device and the other could be interfaced to external eMMC flas...

Page 67: ...0 SD2_DAT1__ SD2_DATA1 P40 SDIO_D1 SDIO_D1 SDIO Data 1 A23 ALT0 SD2_DAT3__ SD2_DATA3 P41 SDIO_D2 SDIO_D2 SDIO Data 2 B22 ALT0 SD2_DAT3__ SD2_DATA3 P42 SDIO_D3 SDIO_D3 SDIO Data 3 U21 ALT0 ENET_CRS_DV_...

Page 68: ...MMC_CK SDMMC_CK SDMMC Clock Signal B13 ALT0 SD3_CMD__ SD3_CMD S36 SDMMC_CMD SDMMC_CMD SDMMC Command signal D15 ALT0 SD3_RST__ SD3_RESET S37 SDMMC_RST SDMMC_RST Reset signal to eMMC device Note 1 The S...

Page 69: ...rection Type Tolerance Description SDIO_D 0 3 Bi Dir CMOS 3 3V 4 bit data path SDIO_CMD Bi Dir CMOS 3 3V Command Line SDIO_CK Output CMOS 3 3V Clock SDIO_WP Input CMOS 3 3V Write Protect SDIO_CD Input...

Page 70: ...eMMC interface on carrier board There is an on module 8 bit 8GB eMMC Bothe the on module and on carrier eMMC be selected as the Boot Device see Section 4 3 Boot Select Edge Golden Finder Signal Name D...

Page 71: ...ins but each device will have its own chip select pin The chip select signal is a low active signal The 4MB onboard SPI NOR flash uses the SPI0 interface with different chip select signal The onboard...

Page 72: ...DAT10__ ECSPI2_MISO P45 SPI0_DIN SPI0_DIN SPI0 Master Data input input to CPU output from SPI device N5 ALT2 CSI0_DAT9__ ECSPI2_MOSI P46 SPI0_DO SPI0_DO SPI0 Master Data output output from CPU input t...

Page 73: ...r Signal Name Direction Type Tolerance Description SPI0_CS0 Output CMOS VDDIO SPI0 Master Chip Select 0 output SPI0_CS1 Output CMOS VDDIO SPI0 Master Chip Select 1 output SPI0_CK Output CMOS VDDIO SPI...

Page 74: ...ription SPI1_CS0 Output CMOS VDDIO SPI1 Master Chip Select 0 output SPI1_CS1 Output CMOS VDDIO SPI1 Master Chip Select 1 output SPI1_CK Output CMOS VDDIO SPI1 Master Clock output SPI1_DIN Input CMOS V...

Page 75: ...as shown below Freescale i MX6 CPU SMARC FiMX6 Edge Golden Finger Net Names Note Ball Mode Pin Name Pin Pin Name P4 ALT3 CSI0_MCLK__ CCM_CLKO1 S38 Audio_MCK AUD_MCLK Master clock output to Audio codec...

Page 76: ...Name Direction Type Tolerance Description I2S0_LRCK Bi Dir CMOS VDDIO Left Right audio synchronization clock I2S0_SDOUT Output CMOS VDDIO Digital audio Output I2S0_SDIN Input CMOS VDDIO Digital audio...

Page 77: ...MX6 CPU SMARC FiMX6 Edge Golden Finger Net Names Note Ball Mode Pin Name Pin Pin Name R1 ALT4 GPIO_17__ SPDIF_OUT S59 SPDIF_OUT SPDIF_OUT Digital Audio Out R2 ALT4 GPIO_16__ SPDIF_IN S60 SPDIF_IN SPDI...

Page 78: ...port The module asynchronous serial port signals have a VDDIO 1 8V or 3 3V level signal swing They can be converted to RS232 level and polarity signals by using a suitable RS232 transceiver Almost al...

Page 79: ...CTS Clear to Send handshake line for SER0 SER1 Port E24 ALT4 EIM_D26__ UART2_TX_DATA P134 SER1_TX SER1_TX Asynchronous serial port data out E25 ALT4 EIM_D27__ UART2_RX_DATA P135 SER1_RX SER1_RX Asynch...

Page 80: ...wire ports data only Edge Golden Finder Signal Name Direction Type Tolerance Description SER 0 3 _TX Output CMOS VDDIO Asynchronous serial port data out SER 0 3 _RX Input CMOS VDDIO Asynchronous seri...

Page 81: ...f the five I2C buses and supports multiple masters and slaves in fast mode 400 KHz operation The I2C_PM is implemented directly from Freescale i MX6 I2C1 interfaces The I2C_HDMI is implemented directl...

Page 82: ...anagement support System configuration management CMOS 1 8V I2C_GP I2C30 General purpose use CMOS VDDIO I2C_LCD I2C31 LCD display support to read LCD display EDID EEPROMs for parallel and LVDS LCD Gen...

Page 83: ...bus clock I2C30_SDA S49 I2C_GP_DAT I2C_GP_DAT General purpose I2C bus data I2C_LCD TCA9546 I2C31_SCL S139 I2C_LCD_CK I2C_LCD_CK LCD display I2C bus clock I2C31_SDA S140 I2C_LCD_DAT I2C_LCD_DAT LCD dis...

Page 84: ...tails are listed in the following table Device Description Address 7 bit Address 8 bit Notes Read Write I2C_PM I2C1 Bus 1 On Semiconductor CAT24C32 EEPROM 0x50 0xA1 0xA0 General purpose parameter EEPR...

Page 85: ...utput V5 ALT0 KEY_ROW4__ FLEXCAN2_RX P146 CAN1_RX CAN1_RX CAN1 Receive input By SMARC hardware specification CAN0 bus error condition signaling should be supported on the Module GPIO8 P116 pin This is...

Page 86: ...Name Direction Type Tolerance Description CAN0_TX Output CMOS VDDIO CAN0 Transmit output CAN0_RX Input CMOS VDDIO CAN0 Receive input 2 1 23 2 CAN1 BUS Signals Edge Golden Finder Signal Name Direction...

Page 87: ...fic alternate functions are assigned to some GPIOs such as PWM Tachometer capability Camera support CAN Error Signaling and HD Audio reset All pins are capable of bi directional operation A default di...

Page 88: ...low output D17 ALT5 NANDF_D3__ GPIO2_IO03 P111 GPIO3 CAM1_RST GPIO3 Camera 1 Reset active low output C18 ALT5 NANDF_D7__ GPIO2_IO07 P112 GPIO4 HDA_RST GPIO4 HD Audio Reset active low output F18 ALT5...

Page 89: ...ity polarity are generally configurable in the i MX6 register set Edge Golden Finder Signal Name Preferred Direction Type Tolerance Description GPIO0 CAM0_PWR Output CMOS VDDIO Camera 0 Power Enable a...

Page 90: ...ough the standard Linux Watchdog API A description of the API is available following the link below http www kernel org doc Documentation watchdog watchdog api txt WDT signals are exposed on the SMARC...

Page 91: ...and pin out Figure 14 JTAG Connector Location and Pinout JTAG functions for CPU debug and test are implemented on separate small form factor connector CN3 JST SM10B SRSS TB 1mm pitch R A SMD Header T...

Page 92: ...MFG_Mode I Pulled low to allow in circuit SPI ROM update 10 GND Ground Ground 2 1 27 Boot ID EEPROM The SMARC FiMX6 module includes an I2C serial EEPROM available on the I2C_PM bus An On Semiconductor...

Page 93: ...and 1GB DDR3 Configuration SMCMXS00 Embedian SMARC FiMX6 Computer on Module with Solo Core and 512MB DDR3 Configuration Version 4 Hardware version code for version in ASCII 00A0 rev A0 Serial Number...

Page 94: ...he SMARC FiMX6 is shown below Freescale i MX6 CPU SMARC FiMX6 Edge Golden Finger Net Names Notes mode Pin Name Pin Pin Name SER3 Debugging Port ALT3 CSI0_DAT14__ UART5_TX_DATA P140 SER3_TX SER3_TX Asy...

Page 95: ...User s Manual v 1 2 2 3 4 Mechanical Drawings The mechanical information is shown in Figure 15 SMARC FiMX6 Mechanical Drawings Top View and Figure 16 SMARC FiMX6 Mechanical Drawings Bottom View Figur...

Page 96: ...omputer on Module User s Manual v 1 2 Figure 16 SMARC FiMX6 Mechanical Drawings Bottom View The figure on the following page details the 82mm x 50mm Module mechanical attributes including the pin numb...

Page 97: ...Embedian Inc 97 SMARC FiMX6 Computer on Module User s Manual v 1 2 Figure 17 SMARC FiMX6 Module Mechanical Outline...

Page 98: ...Inc 98 SMARC FiMX6 Computer on Module User s Manual v 1 2 Top side major component IC and Connector information is shown in Figure 18 SMARC FiMX6 Top side components Figure 18 SMARC FiMX6 Top Side Co...

Page 99: ...99 SMARC FiMX6 Computer on Module User s Manual v 1 2 Bottom side major component IC and Connector information is shown in Figure 19 SMARC FiMX6 Bottom side components Figure 19 SMARC FiMX6 Bottom Sid...

Page 100: ...r the 5mm stack would likely be a standard length When a 1 5mm stack height Carrier board connector is used there shall not be components on the Carrier board Top side in the Module region Additionall...

Page 101: ...holes 82mm x 50mm Module or 7 holes 82mm x 80mm Module depends on the spacer hardware selection See the section below for more information on this 2 3 6 Module Assembly Hardware The SMARC FiMX6 modul...

Page 102: ...r board threaded standoff The SMARC connector board to board stack heights that are available may result in the use of non standard spacer lengths The board to board stack heights available include 1...

Page 103: ...fhdwe com offer M2 5 compatible swaged standoffs Swaged standoffs require the use of a press and anvil at the CM Their use is common in the industry The standoff OD and Carrier PCB hole size requireme...

Page 104: ...5mm 4 3mm Flash Std Black Foxconn AS0B821 S43N H 1 5mm 4 3mm Flash Std Ivory Foxconn AS0B826 S43B H 1 5mm 4 3mm 10 u in Std Black Foxconn AS0B826 S43N H 1 5mm 4 3mm 10 u in Std Ivory Lotes AAA MXM 008...

Page 105: ...d Tan Speedtech B35P101 02123 H 2 76mm 5 2mm 15 u in Std Black Speedtech B35P101 02023 H 2 76mm 5 2mm 15 u in Std Tan Foxconn AS0B821 S78B H 5 0mm 7 8mm Flash Std Black Foxconn AS0B821 S78N H 5 0mm 7...

Page 106: ...n the sections below 2 3 9 Module Cooling Solution Heat Spreader A standard heat spreader plate for use with the SMARC 82mm x 50mm form factor is described below A standard heat spreader plate definit...

Page 107: ...to secure the PCB in the SOC area and compress the TIM The four interior holes that are further from the center allow a heat sink to be attached to the heat spreader plate or they can be used to secu...

Page 108: ...te to be flush with a secondary heat sink Hole size depends on standoffs used Standoff diameter must be compatible with SMARC Module mounting hole pad and hole size 6 0mm pads 2 7mm holes on the Modul...

Page 109: ...r board This connection provides back up power to the module PMIC The RTC is powered via the primary system 3 3V supply during normal operation and via the VBAT power input if it is present during pow...

Page 110: ...he hardware used for testing includes an SMARC FiMX6 module carrier board for SMARC ARM TFT monitor micro SD card and USB keyboard The carrier board was powered externally by a power supply unit so th...

Page 111: ...KB L2 Cache Memory Size 512MB Operating System Ubuntu 14 04 Power States Desktop Idle 100 workload Max power consumption Power Consumption Amp Watts 0 22A 1 1W 0 31A 1 55W 0 42A 2 1W 2 4 6 2 Freescale...

Page 112: ...Ubuntu 14 04 Power States Desktop Idle 100 workload Max power consumption Power Consumption Amp Watts 0 28A 1 4W 0 5A 2 5W 0 7A 3 5W 2 4 6 4 Freescale i MX6 Cortex A9 1GHz Quad Core 1MB L2 Cache With...

Page 113: ...Ubuntu 14 04 Power States Desktop Idle 100 workload Max power consumption Power Consumption Amp Watts 0 28A 1 4W 0 52A 2 6W 0 72A 3 6W 2 4 6 6 Freescale i MX6 Cortex A9 1GHz Quad Core 1MB L2 Cache Wit...

Page 114: ...C to 60 C air temperature without a passive heat sink arrangement Industrial temperature 40o C 85o C is also available with different part number SMARC FiMX6 I 2 5 2 Humidity Operating 10 to 90 RH non...

Page 115: ...an Inc 115 SMARC FiMX6 Computer on Module User s Manual v 1 2 Connector PinOut This Chapter gives detail pinout of SMARC FiMX6 golden finger edge connector Section include SMARC FiMX6 Connector Pin Ma...

Page 116: ...e key 4 on the primary side and 3 on secondary side The Secondary Bottom side faces the Carrier board when a normal or standard Carrier connector is used The SMARC FiMX6 module pins are deliberately n...

Page 117: ...ification The Freescale i MX6 CPU column shows the connection of the CPU signals on the module The format of this column is Ball Mode Signal Name where Signal Name is the chip where the signals are co...

Page 118: ...P7 CSI1_D0 PCAM_D2 E3 CSI_D0P I CSI1 differential data inputs P8 CSI1_D0 PCAM_D3 E4 CSI_D0M I CSI1 differential data inputs P9 GND P Ground P10 CSI1_D1 PCAM_D4 D2 CSI_D1P I CSI1 differential data inp...

Page 119: ...OD Link Speed Indication LED for 100Mbps Could be able to sink 24mA or more Carrier LED current P22 GbE_LINK1000 O OD Link Speed Indication LED for 1000Mbps Could be able to sink 24mA or more Carrier...

Page 120: ...fferential Transmit Receive Negative Channel 1 P27 GbE_MDI1 AIO Qualcomm AR8035 Differential Transmit Receive Positive Channel 1 P28 GbE_CTREF O Qualcomm AR8035 Center tap reference voltage for GBE Ca...

Page 121: ...O_CK C21 ALT0 SD2_CLK__ SD2_CLK O Clock P37 SDIO_PWR_EN B21 ALT5 ENET_TX_EN__ GPIO1_IO28 O SD card power enable P38 GND P Ground P39 SDIO_D0 A22 ALT0 SD2_DAT0__ SD2_DATA0 IO Data path P40 SDIO_D1 E20...

Page 122: ...50 GND P Ground P51 SATA_RX B14 SATA_RXP I Receive Input differential pair P52 SATA_RX A14 SATA_RXM I Receive Input differential pair P53 GND P Ground P54 SPI1_CS0 U6 ALT5 KEY_ROW1__ GPIO4_IO09 O SPI1...

Page 123: ...ENET_TXD0__ GPIO1_IO30 ENET_TXD1__ GPIO1_IO29 IO OD Pulled low by Module OD driver to disable USB0 power Pulled low by Carrier OD driver to indicate over current situation If this signal is used a pu...

Page 124: ...r current situation If this signal is used a pull up is required on the Carrier P68 GND P Ground P69 USB2 Not used P70 USB2 Not used P71 USB2_EN_OC Not used P72 PCIE_C_PRSNT Not used P73 PCIE_B_PRSNT...

Page 125: ...erential PCI Express Reference Clock Signals for Lanes A P85 GND P P86 PCIE_A_RX B2 PCIE_RXP I Differential PCIe Link A receive data pair 0 P87 PCIE_A_RX B1 PCIE_RXM I Differential PCIe Link A receive...

Page 126: ...1 P97 GND P Ground P98 HDMI_D0 K6 N A HDMI_D0P O TMDS HDMI data differential pair 0 P99 HDMI_D0 K5 N A HDMI_D0M O TMDS HDMI data differential pair 0 P100 GND P Ground P101 HDMI_CK J6 N A HDMI_CLKP O H...

Page 127: ...F_D6__ GPIO2_IO06 IO Camera 0 Reset active low output P111 GPIO3 CAM1_RST D17 ALT5 NANDF_D3__ GPIO2_IO03 IO Camera 1 Reset active low output P112 GPIO4 HDA_RST C18 ALT5 NANDF_D7__ GPIO2_IO07 IO HD Aud...

Page 128: ...gement I2C bus clock P122 I2C_PM_DAT G23 ALT1 EIM_D28__ I2C1_SDA IO OD Power management I2C bus data P123 BOOT_SEL0 I SYSBOOT and Line De multiplexer Logic Pulled up on Module Driven by OD part on Car...

Page 129: ...ctive low level sensitive It is de bounced on the Module Pulled up on Module Driven by OD part on Carrier P129 SER0_TX F13 ALT1 SD3_DAT7__ UART1_TX_DATA O Asynchronous serial port data out P130 SER0_R...

Page 130: ...16__ UART4_CTS_B Clear to Send handshake line for SER2 P140 SER3_TX M4 ALT3 CSI0_DAT14__ UART5_TX_DATA O Asynchronous serial port data out P141 SER3_RX M5 ALT3 CSI0_DAT15__ UART5_RX_DATA I Asynchronou...

Page 131: ...MX6 Computer on Module User s Manual v 1 2 SMARC Edge Finger Freescale i MX6 CPU Type Description Pin Pin Name Ball Mode Signal Name P153 VDD_IN P Power in P154 VDD_IN P Power in P155 VDD_IN P Power i...

Page 132: ...t used S5 I2C_CAM_CK IO OD Port3 of TCA9546 Camera I2C bus clock S6 CAM_MCK A17 ALT4 NANDF_CS2__ CCM_CLKO2 O Master clock output for CSI camera support S7 I2C_CAM_DAT IO OD Port3 of TCA9546 Camera I2C...

Page 133: ...19 AFB2_OUT Not used S20 AFB3_IN Not used S21 AFB4_IN Not used S22 AFB5_IN Not used S23 AFB6_PTIO Not used S24 AFB7_PTIO Not used S25 GND P Ground S26 SDMMC_D0 E14 ALT0 SD3_DAT0__ SD3_DATA0 IO 4 bit e...

Page 134: ...SDMMC Command signal S37 SDMMC_RST D15 ALT0 SD3_RST__ SD3_RESET O Reset signal to eMMC device S38 AUDIO_MCK P4 ALT3 CSI0_MCLK__ CCM_CLKO1 O Master clock output to Audio codecs S39 I2S0_LRCK N4 ALT4 CS...

Page 135: ...GP_DAT IO OD Port1 of TCA9546 General purpose I2C bus clock S50 I2S2_LRCK Not used S51 I2S2_SDOUT Not used S52 I2S2_SDIN Not used S53 I2S2_CK Not used S54 SATA_ACT R7 ALT5 GPIO_3__ GPIO1_IO03 O OD Ser...

Page 136: ...a channel differential pairs 1 S64 GND S65 AFB_DIFF1 AA1 ALT0 LVDS1_TX1_P AIO LVDS1 LCD data channel differential pairs 2 S66 AFB_DIFF1 AA2 ALT0 LVDS1_TX1_N AIO LVDS1 LCD data channel differential pai...

Page 137: ...FB_DIFF4 AA3 ALT0 LVDS1_TX3_N AIO LVDS1 LCD data channel differential pairs 4 S76 PCIE_B_RST Not used S77 PCIE_C_RST Not used S78 PCIE_C_RX Not used S79 PCIE_C_RX Not used S80 GND P Ground S81 PCIE_C_...

Page 138: ...implementations leave the two LS bits D0 D1 not connected S94 LCD_D1 P22 ALT0 DISP0_DAT1__ IPU1_DISP0_DATA01 O S95 LCD_D2 V23 ALT0 DISP0_DAT2__ IPU1_DISP0_DATA02 O S96 LCD_D3 P21 ALT0 DISP0_DAT3__ IPU...

Page 139: ...ations leave the two LS bits D8 D9 not connected S103 LCD_D9 T25 ALT0 DISP0_DAT9__ IPU1_DISP0_DATA09 O S104 LCD_D10 R21 ALT0 DISP0_DAT10__ IPU1_DISP0_DATA10 O S105 LCD_D11 T23 ALT0 DISP0_DAT11__ IPU1_...

Page 140: ...ISP0_DAT19__ IPU1_DISP0_DATA19 O S115 LCD_D20 U22 ALT0 DISP0_DAT20__ IPU1_DISP0_DATA20 O S116 LCD_D21 T20 ALT0 DISP0_DAT21__ IPU1_DISP0_DATA21 O S117 LCD_D22 V24 ALT0 DISP0_DAT22__ IPU1_DISP0_DATA22 O...

Page 141: ...TX0_N AIO LVDS0 LCD data channel differential pairs 1 S127 LCD_BKLT_EN T5 ALT5 GPIO_0__ GPIO1_IO00 O High enables panel backlight S128 LVDS1 U3 ALT0 LVDS0_TX1_P AIO LVDS0 LCD data channel differential...

Page 142: ...0 LVDS0_TX3_N AIO LVDS0 LCD data channel differential pairs 4 S139 I2C_LCD_CK IO OD Port2 of TCA9546 LCD display I2C bus clock S140 I2C_LCD_DAT IO OD Port2 of TCA9546 LCD display I2C bus clock S141 LC...

Page 143: ...indication to Module Low indicates lid closure which system may use to initiate a sleep state Carrier to float the line in in active state Active low level sensitive Should be de bounced on the Module...

Page 144: ...e and Carrier power supervisory circuits shall not be enabled while this signal is held low by the Carrier Pulled up on Module Driven by OD part on Carrier S151 CHARGING J23 ALT5 EIM_CS1__ GPIO2_IO24...

Page 145: ...nal S155 FORCE_RECOV D25 ALT5 EIM_D23__ GPIO3_IO23 I Pulled up on Module Driven by OD part on Carrier S156 BATLOW J19 ALT5 EIM_D29__ GPIO3_IO29 I Battery low indication to Module Carrier to float the...

Page 146: ...trol Signals between SMARC Module and Carrier This Chapter points out the handshaking rule between SMARC module and carrier Section include SMARC FiMX6 Module Power Power Signals Power Flow and Contro...

Page 147: ...wn also need to be cared to make all functions work 4 1 SMARC FiMX6 Module Power 4 1 1 Input Voltage Main Power Rail The allowable Module DC input voltage range for SMARC FiMX6 is from 3 0V to 5 25V T...

Page 148: ...flow out of the Module VDD_RTC rail to charge the Super Cap 4 1 4 Power Sequencing The Module signal CARRIER_PWR_ON exists to ensure that the Module is powered before the main body of Carrier circuits...

Page 149: ...IO is depreciated from SMARC 1 1 specification However many users still preferred 3 3V VDD_IO because it is easier for carrier design SMARC FiMX6 supports 1 8V or 3 3V VDD_IO If the Carrier supports o...

Page 150: ...main includes circuits that are active whenever either charger input power and or battery power are available These circuits may include power supply supervisor s battery chargers fuel gauges and depe...

Page 151: ...Embedian Inc 151 SMARC FiMX6 Computer on Module User s Manual v 1 2 Figure 27 System Power Domains...

Page 152: ...R 3 0V 5 25V1 Main power supply input for the module P2 S3 P9 S10 P12 S13 P15 S16 P18 S25 P32 S34 P38 S47 P47 P50 P53 P59 S61 S64 S67 P68 S70 S73 P79 S80 P82 S83 P85 S86 P88 S89 P91 S92 P94 P97 P100 S...

Page 153: ..._PWR_ON O CMOS VDD_IO Signal to inform Carrier board circuits being powered up P126 RESET_OUT O CMOS VDD_IO General purpose reset output to Carrier board P127 RESET_IN I CMOS VDD_IO Reset input from C...

Page 154: ...ve state Pulled up on Module Driven by OD part on Carrier S154 CARRIER_PWR_ON O CMOS VDD_IO Signal to inform Carrier board circuits being powered up S153 CARRIER_STBY O CMOS VDD_IO Module will drive t...

Page 155: ...ven by OD part on Carrier 4 2 4 Special Control Signals TEST SMARC FiMX6 module boots up from an onboard NOR Flash first The firmware u boot in boot rom will read the BOOT_SEL configuration and decide...

Page 156: ...nc 156 SMARC FiMX6 Computer on Module User s Manual v 1 2 4 3 Power Flow and Control Signals Block Diagram Following figures shows the power flow and control signals block diagram Figure 28 Power Bloc...

Page 157: ...le asserts CARRIER_PWR_ON The module signal CARRIER_PWR_ON exists to ensure that the module is powered before the main body of carrier circuits those outside the power and power control path on the ca...

Page 158: ...sources to trigger CPU is suspended wakeup capable peripherals are running while others might be switched off Power rails are available on carrier board peripherals might be stopped by software RUN Ru...

Page 159: ...5 Power Sequences When main power is supplied from the carrier a voltage detector will assert VIN_PWR_BAD signal to tell the module and carrier that the power is good VDD_IO_SEL will be floating on c...

Page 160: ...ollowed by the lower voltages e g 3 3V then 1 8V and so on Peripherals normally require that a lower voltage rails is never present if a higher rail is missing Check the datasheet of all peripheral co...

Page 161: ...em may not provide the shutdown function As it is not permitted that a lower voltage rail is present when a higher voltage rail has been switched off the sequence of shutting down the peripheral volta...

Page 162: ...output RESET_OUT are asserted as long as RESET_IN is asserted If the reset input RESET_IN is de asserted the internal reset and the RESET_OUT will remain low for at least 1ms until they are also de as...

Page 163: ...nation Parallel Termination Notes HDMI_CTRL_DAT 100k pull up to VDD_IO HDMI_CTRL_CK 100k pull up to VDD_IO HDMI_CEC 100k pull up to VDD_IO I2C_PM_DAT 2 2K pull up to 1 8V I2C_PM_CK 2 2K pull up to 1 8...

Page 164: ...3V on the Module x is 0 or 1 Switched 3 3V if a USB channel is not used then the USBx_EN_OC pull up rail may be held at GND to prevent leakage currents VIN_PWR_BAD 100k pull up to VIN PCIE_A_TX 0 1 u...

Page 165: ...econdary side center tap terminations appropriate for Gigabit Ethernet implementations GBE_LINK GBE status LED sinks If used current limiting resistors and diodes to pulled to a positive supply rail T...

Page 166: ...HDMI_CTRL_CK HDMI_CEC Pull ups to VDD_IO on each of these lines is required on the Carrier The pull ups may be part of an integrated HDMI ESD protection and control line level shift device such as th...

Page 167: ...d stage bootloader from selected boot devices The BOOT_SELx pins are weakly pulled up on the Module and the pin states decoded by module logic The Carrier shall either leave the Module pin Not Connect...

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