Manual P104-DIO-96
4
Chapter 1: Introduction
Each I/O line of this board is buffered and capable of sourcing 32mA or sinking 64mA. The board
simulates Programmable Peripheral Interface chips (PPI) to provide a computer interface to digital I/O
lines. Each PPI supports two 8-bit ports (A, B) and two 4-bit ports (C
hi
, C
low
). Each port can be configured
to function as either inputs or output latches. The I/O line buffers (types 74ABT240 and 74ABT245) are
configured automatically by hardware logic for input or output according to the PPI Control Register
direction software assignment.
The board may be shipped with a register map optimized for a higher speed than the pure i8255
port/address map. See the Programming section for an explanation of how a 25% increase in I/O speed
is achieved.
Outputs of the I/O buffers are pulled up through 10K
Ω
resistors to +5VDC. On power-up all I/O pins are
inputs. This means that the lines are at a logic HIGH. The user may request the factory to remove these
10K
Ω
resistors so that the I/O lines will not be driven on power-up (10 uA leakage per pin).
I/O wiring connections are via 50-pin headers on the board. This provides compatibility with OPTO-22,
Gordos, Potter & Brumfield, Western Reserve Controls, etc. module mounting racks. Every second
conductor of the flat cables is grounded to minimize crosstalk. If needed for external circuits, +5VDC
power is available on each I/O connector at pin 49. If you use this power, we recommend that you include
a 1A fast blow fuse in your circuits in order to avoid possible damage to the host computer.
The board occupies 32 bytes within the PCI I/O space. The base address is assigned by the system.
Refer to the Option Selection Section of this manual for a detailed description.
