Manual P104-DIO-96
13
The board is designed to use each of these PPI's in mode 0 wherein:
a.
There are two 8-bit ports (A and B) and two 4-bit ports (C Hi and C Lo).
b.
Any port can be configured as an input or an output.
c.
Outputs are latched.
d.
Inputs are not latched.
Each PPI contains a control register. This Write-only, 8-bit register is used to set the mode and direction
of the ports. At Power-Up or Reset, all I/O lines are set as inputs. Output buffers are automatically set by
hardware logic according to the control register states. Control registers are located at base addresses
+3, +7, +B, and +F. Bit assignments in each of these control registers are as follows:
Bit
Assignment
Function
D0
Port C Lo (C0-C3)
1 = Input, 0 = Output
D1
Port B
1 = Input, 0 = Output
D2
Backward Compatible
Must be 0
D3
Port C Hi (C4-C7)
1 = Input, 0 = Output
D4
Port A
1 = Input, 0 = Output
D5,D6
Backward Compatible
Must be 0
D7
Mode Set Flag & Tristate
1 = Active
Table 5-2:
Control Register Bit Assignments
Note
Because all I/O pins are buffered, the 8255 individual bit control feature is not available. The hardware
uses the control registers to manage buffer direction on this board.
The board emulates four Intel 8255 PPIs. The bit assignments and functionality of the control register has
been kept to maintain backward compatibility with existing software. The emulated 8255 chips differ from
the original in that when a port is configured to be outputs, the I/O pins default to a HIGH state rather than
a LOW state. A port that is programmed to be inputs may have a value written to it. A READ of the port
will return the state of the I/O pins in that case. When that port is configured to be an output latch the
value previously written to it will be driven on the I/O pins.
The board will occupy two spaces in memory. One space is I/O mapped and burst READs or WRITEs will
not work. The other space is memory mapped and should be found below the 1 megabyte boundary (to
facilitate DOC programs) and bursts of four double words are possible. The PCIFIND.EXE program will
display the board’s locations in memory.
The user may specify one of two register mappings (see the Base Registers table in the Programming
chapter): 8255 standard, or an enhanced speed map. The latter allows the user to read from or write to
more ports with a single operation (32 bits versus 24 bits).
Because many motherboard’s reset circuits do not accurately wait for the 3.3V power supply to finish the
power-on sequence, before using the board at each power-up it is necessary to issue a single “Write to
Base +1F” to “Reset” the onboard circuitry.
