eMagin Corporation
SXGA120-120 Reference Board
D01-500947-07 Rev A
SXGA120120 Design Reference Board User
’
s Manual
22
7. FPGA
FPGA Register Map
8. REVISION HISTORY
Revision Level
ECN
Date
Description
1
07/23/08
Initial Release
2
08/14/08
Included new software features. (Gamma Table)
3
10/21/08
New Rev. 2 Drive Board
4
9/10/09
Updated Software Version Number.(V1.4 to V1.6)
5
2/18/2010
New Gamma Functions added.
6
12/17/2010
Updated FPGA Register Map
7
3/27/2015
Added jumpers and slide switch description (p 5 & 6)
A
000904
01/28/2020
Changed SXGA to SXGA120. Misc typo corrections
I2C Slave Address : 010110X
Address
(Hex)
Name
Access
Bit Name
Bit #
Reset
Value
(Hex)
Description
00
STATE
R
REV
2-0
0
Silicon Revision Number
Clock out polarity
0 = positive edge, 1 = negative edge
RESERVED
6
0
Do not use
Interlaced video enable
0 = progressive video, 1 = Interlaced video
Input video resolution
0 = SXGA, 1 = DVGA
STARTX
3-0
6
Line data start position (range 0 to C)
02
ADDR
R/W
7-0
0
Write address for LUT template
03
WRDATA[7:0]
7-0
0
Write LSB data for LUT template with WRDATA write and auto address
increment
04
WRDATA[9:8]
1-0
0
Write MSB date for LUT template
LUT update ready flag (LUT template write disable when "1")
0 = LUT not ready, 1 = New LUT is ready for update
VSYNC polarity
0 = negative sync, 1 = positive sync
HSYNC polarity
0 = negative sync, 1 = positive sync
Ramp generator enabl
0 = disable, 1 = enable
Ramp start position (16 SCLK to 48 SCLK after HSYNC rising edge)
10=16 SCLK, 11=17 SCLK, … 20=32 SCLK, … 30=48 SCLK
0
INTER
5
0
DVGA
01
VIDMODE
R/W
CKOPOL
7
WRDATA
R/W
05
LUTRDY
R/W
1
HSPOL
0
1
4
0
LUTRDY
0
0
06
SYNCPOL
R/W
VSPOL
1
07
RAMPCTL
R/W
RAMPEN
6
0
RAMPST
5-0
20
