User Guide CCM-BOOGIE • High Performance Core
TM
2 Duo 3U
CompactPCI
®
CPU Board
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Main Memory
The CCM-BOOGIE features two channels of DDR3 SDRAMs. One channel is realized with 8 memory
devices soldered to the board (Memory Down) and delivers a capacity of up to 4GB with a clock
frequency of 1066MHz (PC3-8500).
The 2
nd
channel provides a socket for installing a 204-pin SODIMM module thus allowing a simple
expansion of system memory (max. module height = 1.25 inch). Supported are unbuffered DDR3
SODIMMs (V
CC
=1.5V) without ECC featuring on-die termination (ODT), according the PC3-6400 or
PC3-8500 specification. Minimum module size is 256MB; maximum module size is 4GB.
Due to the video requirements of the GS45 chipset, it is recommended to add a SODIMM module
with same size as the Memory Down to get best performance (some of the system memory is
dedicated to the graphics controller). This typically results in a size of 2x1GB of memory which is
recommended to run the operating systems Windows 2000, Windows XP or Windows Vista.
The GS45 chipset supports symmetric and asymmetric memory organization. The maximum memory
performance can be obtained by using the symmetric mode. When in this mode, the GMCH accesses
the memory channels in an interleaved way. Since the GS45 supports Intels Flex Memory Technology,
interleaved operation isn't limited to systems using memory channels of equal capacity. In the case of
unequal memory population the smaller memory channel dictates the address space of the interleaved
accessible memory region. The remainder of the memory is then accessed in non-interleaved mode.
In asymmetric mode the memory always will be accessed in a non-interleaved manner with the
drawback of less bandwidth. The only meaningful application of asymmetric mode is the special case
when only one memory channel is populated (i.e. the SODIMM socket may be left empty).
The contents of the SPD EEPROM on the SO-DIMM is used by the BIOS at POST (Power-on Self Test)
to get any necessary timing parameters to program the memory controller within the chipset.
