Efinix Trion T120 BGA324, User Manual

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Trion T120 BGA324 Development Kit User Guide
Headers P5 and P7 (MIPI Transmitters)
P5 and P7 are dedicated MIPI CSI-2 transmitter high-speed interface connectors that support
1 clock lane and 4 data lanes. These headers also include optional supply pins VSUP1,
VSUP2, VSUP3, as well as five 1.8 V or 3.3 V GPIO pin (user selectable). You can use these
connectors to attach a camera connector daughter card.
Note: P5 and P7 are located on the bottom of the board.
Table 9: MIPI Transmitter Channel 0 (P7) and Channel 1 (P5)
where x is 1 or 0
Pin
Number
Signal Name Description Pin
Number
Signal Name Description
1 VSUP1 Voltage supply 1 2 MIPI x _TXD_P0
3 VSUP2 Voltage supply 2 4 MIPI x _TXD_N0
Differential MIPI
Transmitter Channel
Lane 0
5 GND Ground 6 GND Ground
7 NC 8 MIPI x _TXD_P1
9 NC
No Connect
10 MIPI x _TXD_N1
Differential MIPI
Transmitter Channel
Lane 1
11 GND Ground 12 GND Ground
13 NC 14 MIPI x _TXD_P2
15 NC
No Connect
16 MIPI x _TXD_N2
Differential MIPI
Transmitter Channel
Lane 2
17 GND Ground 18 GND Ground
19 NC 20 MIPI x _TXD_P3
21 NC
No Connect
22 MIPI x _TXD_N3
Differential MIPI
Transmitter Channel
Lane 3
23 GND Ground 24 GND Ground
25 NC 26 MIPI x _TXD_P4
27 NC
No Connect
28 MIPI x _TXD_N4
Differential MIPI
Transmitter Channel
Lane 4
29 GND Ground 30 GND Ground
31 NC 32 USER_LED0 (P5)
PMOD_A_IO4 (P7) 1.8 or 3.3 V GPIO
33 NC
No Connect
34 USER_LED1 (P5)
PMOD_A_IO5 (P7) 1.8 or 3.3 V GPIO
35 GND Ground 36 GND Ground
37 VSUP3 Voltage supply 3 38 USER_LED02 (P5)
PMOD_A_IO6 (P7) 1.8 or 3.3 V GPIO
39 GPIOT_RXN16 (P5)
GPIOT_RXN15 (P7) 1.8 or 3.3 V GPIO 40 USER_LED3 (P5)
PMOD_A_IO7 (P7) 1.8 or 3.3 V GPIO
Header J1 (12 V Power)
J1 is a 12 V DC power supply input jack. J1 supplies power to regulators on the board that
power the T120F324I4 FPGA. The maximum current supply to this input jack is 10 A.
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