EFA P5V580 VP3, Manual, Page: 39 / 55

Chapter 3
3 -7
•
C8000 ~ CBFFF
Shadow ...
DC000~DFFFF
Shadow:
Enabled
Disabled
Optional ROM will be copied to RAM by 16K
bytes per unit.
The shadow function is disabled.
•
Delay For HDD
(Secs)
0 ~ 15
Set the predelay time for hard disk to be ready
to be accessed by the system.
3.5 Chipset Features Setup
ROM PCI/ISA BIOS (2A5LEQ19)
CMOS SETUP UTILITY
CHIPSET FEATURES SETUP
Bank 0/1 DRAM Timing : 70ns On Chip USB : Disabled
Bank 2/3 DRAM Timing : 70ns
Bank 4/5 DRAM Timing : 70ns
SDRAM Latency length : 3
DRAM Read Pipeline : Enabled
Sustained 3T Write : Enabled
L2 Cache Pipeline : Enabled
Read Around write : Disabled
Cache Timing : Fast
Video BIOS Cacheable : Enabled
ESC: Quit
↑↓→←
: Select Item
System BIOS Cacheable : Enabled F1 : Help PU/PD/+/- : Modify
Memory Hole At 15Mb Addr : Disabled F5 : Old Values (Shift)F2: Color
AGP Aperture Size (4~256) : 64M F7 : Load Setup Defaults
AGP-2X mode : Disabled
Figure 3-5 Chipset Feature Setup
The following pages tell you the options of each item and describe the
meaning of each option.
Item Option Description
•
Bank 0/1, 2/3, 4/5
DRAM Timing
60ns
70ns These items are of selected EDO DRAM
read/write timing. You must ensure that
your DIMMs are as fast as 60ns, otherwise
you have to select 70ns.
•
SDRAM Latency
length
3
2 Define the CLT timing parameter of
SDRAM expressed in 66MHz clocks,
Latency Time = 2 clocks
Latency Time = 3 clocks
•
DRAM Read
Pipeline
Enabled
Disabled Enable DRAM Read Pipeline
Disable DRAM Read Pipeline
•
Sustained 3T Write
Enabled
Disabled Enable Sustained 3T Write
Disable Sustained 3T Write
•
L2 Cache Pipeline
Enabled Enable L2 Cache Pipeline