P5HX-A
User’s Manual 1-28
Peer Concurrency
- Determines the CPU allowed to run DRAM/L2 cycles or not
when non-PHLD PCI master devices are targeting peer device . The available
options are:
•
Enabled (default)
•
Disabled
Chipset Special Features
- Enable/Disable chipset special features . The
available options are:
•
Enabled (default)
•
Disabled
DRAM ECC/PARITY Select
- Allows users to configure the DRAM error check
method. The available options are:
•
Parity (default)
•
ECC
Memory Parity/ECC Check
- Determines the memory check function
nabled” or
isabled” and the function can enable only under the DRAM with
parity bit support . Otherwise , please select
uto” . BIOS can auto-detect
whether DRAM support DRAM ECC/Parity function . The available options are:
•
Disabled (default)
•
Enabled
•
Auto
L2 Cache Cacheable Size
- Determines the L2 cache cacheable size 64MB or
512MB . The available options are:
•
64MB (default)
•
512MB
Chipset NA# Asserted
- Determines to enable the Next Address (NA#) cycle or
not . The available options are:
•
Enabled (default)
•
Disabled