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Precharge to Active (5T)
This item is used to designate the minimum Row Precharge time of the
SDRAM devices on the module.
DRAM must continually be refreshed or it will lose its data. Normally, DRAM is
refreshed entirely as the result of a single request. This option allows you to de-
termine the number of CPU clocks allocated for the Row Address Strobe (RAS) to
accumulate its charge before the DRAM is refreshed. If insufficient time is allowed,
refresh may be incomplete and data lost.
Active to Precharge (7T)
This item specifies the number of clock cycles needed after a bank active
command before a precharge can occur.
Active to CMD (5T)
This item specifies the minimum required delay between activation of different
rows.
DRAM Burst Len (4)
This item describes which burst lengths are supported by the devices on the
motherboard. 1 level can provide faster performance but may result in instabil-
ity whereas 8 level gives the most stable but slowest performance.
DRAM Command Rate (2T command)
This item enables you to specify the waiting time for the CPU to issue the next
command after issuing the command to the DDR memory. We recommend
that you leave this item at the default value.
Write Recovery Time (3T)
This item controls the timing between write and precharge command.
Press <Esc> to return to the Advanced Chipset Features screen.
AGP & P2P Bridge Control
Scroll to this item and press <Enter> to view the following screen:
Phoenix – AwardBIOS CMOS Setup Utility
AGP & P2P Bridge Control
Item Help
AGP Aperture Size
[128 MB]
AGP
Mode
[4X]
AGP Fast Write
[Disabled]
AGP 3.0 Calibration Cycle
[Enabled]
Menu Level
↑
↓
→
←
: Move
Enter : Select
+/-/PU/PD:Value:
F10: Save ESC: Exit F1:General Help
F5:Previous Values
F6:Fail-Safe Defaults
F7:Optimized Defaults