Chapter 3
H77H2-M4 USER MANUAL
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Active to Active Delay (tRRDmin) (4)
This item controls the ACTIVE bank x to ACTIVE bank y in memory clock cycles.
Read CAS# Precharge (tRTP) (5)
This item controls the Read to PRECHARGE delay for memory devices, in memory
clock cycles.
Four Active Window Delay (tFAW) (20)
This item controls the four bank activate time in memory clock cycles.
Intel Graphics Configuration
This item shows the information of Intel Graphics Configuration.
Graphics Core Ratio Limit (18)
This item shows the graphic core ratio Limit value.
Graphics Voltage(1/256V) (0)
This item shows the current graphics voltage.
Press <Esc> to return to the M.I.B III Menu page.