Chapter 3
A75F2-A2 USER MANUAL
35
CPU Configuration
The item in the menu shows the CPU.
Main
Advanced
Chipset M.I.B III Boot Security Save & Exit
Enter/Dbl Click : Select
+/- : Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
ESC/Right Click: Exit
F4: Save & Exit
mn
/Click: Select Item
lk
: Select Screen
Enabled/disabled C6
CPU Configuration
Socket0: AMD A8-5500 APU with Radeon(tm) HD Graphics
Max Speed: 3200 MHZ Intended Speed: 3200 MHZ
Microcode Patch Level: 600110f
-- Cache par Core --
L1 Instruction Cache: 64 KB/2-way
L1 Data Cache: 16KB/4-way
L2 Cache: 2048 KB/16-way
No L3 Cache Present
C6 Mode
Enabled
CPB Mode Disabled
AMD C&Q Enabled
Microcode Patch Level (600110f)
This item shows the Microcode revision.
L1 Instruction Cache (64KB/2-way)
This item shows CPU L1 Instruction Cache.
L1 Data Cache (16KB/4-way)
This item shows CPU L1 Data Cache.
L2 Cache (2048 KB/16-way)
This item shows CPU L2 Cache.
AMD C&Q (Enabled)
This item enables or disables the CPU C&Q Function.
C6 Mode (Enabled)
This item enables or disables the C6 mode.
CPB Mode (Disabled)
This item is used to set the CPB mode.
Max Speed (3200 MHz) Intended Speed (3200 MHz)
This item shows the maximum speed of the CPU.