Chengdu Ebyte Electronic Technology Co.,Ltd
ECAN-W01S User
Manual
Copyright
©2012–2022, Chengdu Ebyte Electronic Technology
Co.,Ltd
4.3. Features
4.3.1. CAN filtering
CAN filtering is divided into software filtering and hardware filtering.
4.3.1.1. Software filtering
The upper limit value and lower limit value of received extended frame ID set jointly determine the range of
extended frame ID to be received; A total of three sets of ID filtering can be set.
4.3.1.2. Hardware filtering
There are as many as 28 filter groups (14 for each channel) in the module. By setting filter
groups, each CAN node can receive messages that conform to the filter rules. Messages that do
not conform to the filter rules are discarded by hardware without software intervention. Each
filter bank consists of two 32-bit registers CAN_ FxR0 and CAN_ FxR1 composition. The bit width
of the filter group can be configured as one 32-bit filter or two 16 bit filters. Each filter
group can be configured as masked bit or identifier list mode, and each filter group can be enabled
or disabled.
In the masked bit mode, the two registers are respectively the identifier register and the
masked register, which need to be used together. Each bit of the identifier register indicates
that the expected value of the corresponding bit is explicit or implicit, and each bit of the
masked register indicates whether the expected value of the corresponding identifier register
bit needs to be consistent.
32-bit shielded bit mode
Identifier
register
CAN_
FxR1[31:24]
CAN_ FxR1[23:16]
CAN_
FxR1[15:8]
CAN_ FxR1[7:0]
Masked
bit
register
CAN_
FxR2[31:24]
CAN_ FxR2[23:16]
CAN_
FxR2[15:8]
CAN_ FxR2[7:0]
mapping
STID[10:3]
STID[2:0]
EXID[17:13]
EXID[12:5]
EXID[4:0]
IDE
RTR
0
In identifier list mode, both registers are used as identifier registers, and each bit of the
received message identifier must be consistent with one of the registers to pass the filtering.
32 bit identifier list
Identifier
register
CAN_
FxR1[31:24]
CAN_ FxR1[23:16]
CAN_
FxR1[15:8]
CAN_ FxR1[7:0]
Masked
bit
register
CAN_
FxR2[31:24]
CAN_ FxR2[23:16]
CAN_
FxR2[15:8]
CAN_ FxR2[7:0]
mapping
STID[10:3]
STID[2:0]
EXID[17:13]
EXID[12:5]
EXID[4:0]
IDE
RTR
0
In the 16 bit mode, the register group is divided into four registers. The mask bit mode of each
