9 Appendix
9.1 Data image of the technology modules
XI/ON: XNE-GWBR-2ETH-MB
10/2011 MN05002008Z-EN
www.eaton.com
177
2,3
PWMx_LOGMSG
0
The messages in the MSG-bits (MSG for
PWMx) in the Process input / check-back
interface are active.
1
With a change from 0
→
1 the MSG data are
held and actual incoming messages are
stored to register REG_PWMx_LOGMSG.
Before switching to REG_PWMx_LOGMSG,
this register is set to "0".
With a change from 1
→
0, all data from
REG_PWMx_LOGMSG are copied to the
MSG-bits in the Process input / check-back
interface.
PWMx_SFKT_DISABLE
0
Enable the special function of input Zx
depending on the parameterization.
1
Disable the special function of input Zx
depending on the parameterization.
PWMx_SW_LR
0
Not activated
1
A latch retrigger has to be executed at
counter PWMx with a change from 0
→
1.
PWMx_SINGLE
0
Continuous enabling of PWM
1
Single enabling of PWMx
4
SET_ Dx
0
Clear bit Dx
1
Set bit Dx
SET_ Px
0
Clear bit Px
1
Set bit Px
Register access
5
AUX_REG1_ WR_EN
...
AUX_REG3_ WR_EN
0
Disabling the writing of register data with the
register contents in AUX_REGx_WR_DATA.
This option avoids an unintentional writing to
registers in the Register interface.
1
Writing of the Register interface with the
register contents in AUX_REGx_WR_DATA is
enabled.
Table 81:
Process output
data / control
interface of
XNE-2CNT-
2PWM
Byte Bit
Value
Meaning
