EAI TR-20 Operator'S Reference Manual Download

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Summary of Contents for TR-20

Page 1: ...COMPUTER DPERATDR S REFERENCE HANDBODK ELECTRONIC ASSOCIATES 1NC 1964 PR1NTED IN U S A PUBL NO 00 800 2003 1 JUNE 1967...

Page 2: ...title or footnote all are maintenance handbooks Note that maintenance handbooks directly applicable to a particular system are normally supplied with the system Title Handbook of Analog Computation TR...

Page 3: ...ng the required information will speed the processing of your requests and aid in assuring that the correct items are supplied It is the policy nf Electronic Associates Inc to supply equipment pattern...

Page 4: ...putation Center U S Route No 1 Princeton New Jersey P O Box 582 Tel 609 452 2900 Los Angeles Computation Center 1500 East Imperial Highway EI Segundo California Tel 213 322 3220 TWX 910 348 6284 San F...

Page 5: ...ls EAI 00 342 0572 0 These labels may be attached to the connector blocks to identify the computing components associated with a particular problem DATE 3 30 65 MANUAL TITLE TR 20 COMPUTER OPERATORS R...

Page 6: ...put Voltage Bi Polar 29 8 LOG X DFG AND 1 2 LOG X DFG 29 a General Description 29 E Patching 32 9 VARIABLE DIODE FUNCTION GENERATOR GROUPS 2 645 AND 2 713 32 a General Description 32 b Setup Procedure...

Page 7: ...3 Using Repetitive Operation 54 12 DISPLAY NETWORKS 54 APPENDIX I COMPUTER SYMBOLS AI l APPENDIX II CIRCUITS USING COMPUTATIONAL COMPONENTS AII l APPENDIX III AMPLIFIER CIRCUITS FOR SIMULATING TRANSFE...

Page 8: ...Patching an Amplifier as an Integrator Showing Simplified Schematic of an Integrator Network Patching an Amplifier to a Rep Op Integrator Showing Simplified Schematic of Integrator Network Quarter Sq...

Page 9: ...on Setup Patching 44 Relay Comparator Simplified Diagrams and Setup Patching 48 40 538 Electronic Comparator Unit 49 Comparator Unit Functional Block Diagram 51 Electronic Switch Unit Functional Block...

Page 10: ...ce will also oscillate if the temperature of the coolant at the exhaust port of a con denser rises exponentially to a steady value then so will the voltage representing it on the computer It can be sa...

Page 11: ...accomplished away from the com puter The problem is placed on the computer by inserting the patch panel and ad justing the problem parameters to the value of the first case to be investigated Selected...

Page 12: ...t terminations for the unit The computing components are inter connected by placing patch cords or bottle plugs between the appropriate input and output ter minations Most TR 20 s are equipped with a...

Page 13: ...Figure 1 The TR 20 Desktop Analog Computer with Display Units 4...

Page 14: ...tor Group Consists of Variable Diode Function Generator Variab1e Diode Function Generato VDFG Readout Module Variable Diode Function Generator Group Consists of Variab1e Diode Function Generator Varia...

Page 15: ...ctronic Comparator POWER AND REFERENCE SUPPLIES Regulated Power Supply Reference Regulator Dual DC Amplifier OPTIONAL COMPONENTS AND ACCESSORY EQUIPMENT Repetitive Operation Expansion Group Consists o...

Page 16: ...Cable Pre Patch Panel Rep Op Slave Panel AUXILIARY EQUIPMENT VARIPLOTTER Repetitive Operation Display Unit MODEL NUMBER 12 987 2 475 2 448 13 017 510 038 100 007 51 039 51 040 5 235 20 567 1110 The op...

Page 17: ...HOLD OPER switch to the RESET osition Initially the amplifier over load alarm system will be triggered due to transients after a few seconds the over load indication should cease d Amplifier Balance...

Page 18: ...l I Figure 2 Inserting the Pre Patch Panel 9...

Page 19: ...1 GAIN I 1 b AN INVERTER GAIN OF 0 1 y AMPLIFIER I 10 10 AMPLIFIER 2 10 O PATCHING WITH BOTTLE PLUGS X Z X y y C A SUMMER Z O I X Y Z A GAIN OF I A 10 d A HIGH GAIN AMPLIFIER PATCHED FOR GAINS OF 0 1...

Page 20: ...NULL POT REFERENCE SELECTOR SWITCH VOLTMETER FUNCTION SWITCH Figure 4 The TR 20 Control Panel VOLTMETER ANGE SWITCH 11...

Page 21: ...the problem patching the problem operation or the computing components Usually no harm is done to the equipment by short term overloads unless they are caused by excessively high voltages other than t...

Page 22: ...put monitoring or balancing Connected to the wiper of the AMPL SEL sWitch facilitates connecting any amplifier output to external monitoring or measuring equipment Indicate an overload in the associat...

Page 23: ...EF IAMPL SEL S6 a SAL POSITION IJ 0 IAMPL rn OUT 0 0 INULL I 0 IAMPL I J2 0 Q IpOT BUS 10 0 IBALI ill VOLTMETER 0 FUNCTION SWITCH SI R8 8 2K OJ 10FFI 0 g REF VOLTMETER IAMPL SELl RANGE SWITCH S6 b AMP...

Page 24: ...ION R9 2 2K r I I r 1 II IOV I I I 0 5QJ VOLTMETER II 6_ IOV O IOV FUNCTION SWITCH I r SI RIO 2K S3 R9 2 2K I IVM I I INULL I 0 IAMPL I T BUS I0 0 IBAL I o S3 INULLI POT RIO READOUT SWITCH ATTEN 12 26...

Page 25: ...e polarity of the unknown voltage This null comparison method of voltage measurement is accurate to within p l of full scale An important feature of the method is that no current is drawn from the sou...

Page 26: ...rn 5000 ohm potentiometers The groups are listed below GROUP NO OF POTS TYPE OF POT DIAL REMARKS 42 183 2 Carbon Uncalibrated Does not have Readout Switches 42 187 2 Carbon Unc a1i brated Has Readout...

Page 27: ...7b Depressing the pushbutton switch applies 10 volts to the top of the potentiometer and connects the loaded wiper to the pot bus for measuring purposes Note that the lower end of the attenuator is n...

Page 28: ...TTEN 42 188 L J POT BUS TO SWITCHES OF TO READOUT ALL ATTENUATOR CIRCUITS GROUPS 0 ATTENUATORS SIMPLIFIED SCHEMATIC x RI RT Ein KE in R T T HI RT K X Y Y L RI LO T Y X K Ein 0 KEin K X Y Y Y b GROUNDE...

Page 29: ...input impedance Using Equatio 2 1 as the basis of discussion the following sub paragraphs describe the various u s 2 S of the opera tiona 1 amplifier When the same C 2 1ue resis tor is used for both...

Page 30: ...Figuye 8 Operational Amplifier Simplified Block Diagram 20...

Page 31: ...ance l pC and Z is a resistor the Easic operational amplifier relationship n Equation 2 1 becomes E n e o pRC 1 t RC So e dt n An indefinite number of inputs may be applied to produce the time integr...

Page 32: ...rk contains the passive elements and control circuits necessary to form two integrators The Model 12 1116 is supplied with computers that are not equipped for repetitive operation The Model 12 1115 is...

Page 33: ...712 DC AMPLIFIER PART OF 12 1116 INTEGRATOR NETWORK INTEGRATOR OUTPUTS B SJ IC DUAL INT NET 12 1116 10K KI 10K I I I I I I I 10 MFD K2 INTERNAL FROM RESET BUS J CONNECTION FROM OPERATE BUS Figure 9 Pa...

Page 34: ...next solution Patching and a brief description of these spe ial situations is provided in the appendix 2 Integrator Network 12 1115 This network differs from th network pre viously described principal...

Page 35: ...SJ DUAL INT NET 12 1115 50K RESET 10 MFO lA o if J _ _ _ _ I 0 02 MFD KI K3 CRI CR2 FROM RESET BUS FROM OPERATE BUS FROM TIME SCALE BUS Figure 10 Patching an Amplifier to a Rep Op Integrator Showing...

Page 36: ...quarter square multi plier are referred to the TR 20 Maintenance Manual b Multiplication The general configuration of the quarter square multiplier is shown in Figure lla The DFG s contain biased diod...

Page 37: ...1 DFG xo x X x 8 0 So V YO IN Y O y DFG Y J IN R65 3550 Y y 0 0 MULT MULT 7 045 7 045 o SIMPLIFIED DIAGRAM OF UNIT b MULTIPLIER PATCHING 0 X X S 8 0 xv X X 10 y y y c SYMBOL Figurf 11 Quarter Square M...

Page 38: ...he dividend A to avoid overloads in the output amplifiers The divisor B must not change sign It must not go to zero for this implies an indeterminate or infinite quotient The circuit requires that the...

Page 39: ...in Figure 14 to generate 10 from an input voltage X where 10 X 10 When X is negative the upper DFG conducts and pro duces an output of X2 l0 from amplifier 1 the lower DFG does not conduct When X is...

Page 40: ...ultiplier INa So 0 R INO So 0 x2 DFG 16 101 1 1 X2DF INPUTS t R51 J A A 3550 2 50 R5 35 x 2 DF INPUTS R53 AAA vv 3550 Q SIMPLIFIED DIAGRAM OF UNIT X IN X2 DFG IN X 5 X2 10 0 R IN X2 y DFG y IN 5 _y2 1...

Page 41: ...0 IN X2 S B 0 X2 X OFG 10 Rf 3550 i IN X2 S B 0 OFG 0 Figure 14 Generating Tfor 10 X 1 0 10 31...

Page 42: ...o 0 0 R24 5K LOGX OF 16 126 o SIMPLIFIED DIAGRAM OF UNIT X Y IN S 0 0 0 IN S 0 OG X DFG 16 126 IN X 5 lOG 10 lOX 0 5l0G10 10Y b TY P ICAl PATCH I NG C SYMBOLS Figure 15 Patching the Log X JJFG s 9 VAR...

Page 43: ...154 1 2 713 1 16 156 1 16 310 2 713 2 16 310 16 154 1 2 645 0 16 304 1 16 308 16 306 1 2 645 1 16 304 1 16 308 2 645 2 16 308 16 306 1 15 t READOUT MODULES VDFG UNITS Figure 16 VDFG Mounting Location...

Page 44: ...case 2 6 volts 4 Re connect amplifier 1 to the IN terminal and adjust the setup pot to provide an input of 1 volt Adjust the 1 volt pot until the correct output voltage is reached 3 3 volts in this c...

Page 45: ...l r r l IOK I I 0 2 0 1 __ 1 L ___________ v OFG 16 310 v OFG 16 1 6 3550 3550 O SIMPLIFIED SCHEMATIC x 02 v OFG 16 310 b PATCHING x f x IN B 82 VDFG I c PATCHING SYMBOL Figure 17 VDFG Patching o f x...

Page 46: ...UT 10 O SAMPLE FUNCTION b TABLE OF FUNCTION VALUES IN f VDFG c SETUP PATCHING INPUT INPUT ADJUST OUTPUT 0 PARALLAX 2 6 1 IV 3 3 2 2V 4 0 3 3V 5 0 4 4V 5 0 5 5V 5 7 6 6V 5 7 7 7V 4 6 8 8V 4 2 9 9V 3 0...

Page 47: ...of the diode cha racteristic curve With a feedback resistor of lOOK this current contributes 0 10 volt to the DFG output This is relatively easy to measure To minimize interaction between the function...

Page 48: ...IN VDFG TO OUTPUT MONITORING CIRCUIT 8 g O BREAKPOINT SETUP PATCHING PREFERRED I 10 0 Q IN REMAINDER O CIRCUIT SAME AS ABOVE b BREAKPOINT SETUP PATCHING ALTERNATE METHOD Figure 19 Breakpoint Setup Pa...

Page 49: ...plus the center slope Hence except for the center slope any slope may exceed 1 volt per volt as long as the change in slope between successive seg ments does not 3 Sample Function Setup Procedure The...

Page 50: ...50 o TABLE OF FUNCTION VALUES b BREAKPOI NT LOCATION CURVE I ENDPOINT A BREAKPOINTS c PLOT OF DESIRED FUNCTION fIX 0 00 81 9 3 9 93 9 36 3 67 1 69 0 89 1 56 3 20 6 75 12 00 _______ CURVE BEFORE TRIMMI...

Page 51: ...e slope pot 2 fully counter clockwise and continue alternating the slope pots in this manner This step helps prevent amplifier overload and aids in identifying the breakpoints during the setup procedu...

Page 52: ...10 42 TO PLOTTER X INPUT IN VDFG Figure 21 Breakpoint Location Plot Patching...

Page 53: ...ot look like the desired curve but it enables one to check at a glance that the breakpoints are properly located To make this plot adjust the DFG input voltage to XII the endpoint of the interval of i...

Page 54: ...UTPUT MONITORING CIRCUIT FEEDBACK POT SEE TEXT o 0 050 D a FUNCTION SETUP PATCHING PREFERRED I 10 0 Q REMAINDER OF CIRCUIT SAME AS ABOVE b FUNCTION SETUP PATCHING ALTERNATE METHOD Figure 22 Function S...

Page 55: ...back pot 17 as shawn in Figure 22a and plot the entire curve as done prev iously in Sub paragraph 4 j 6 Amplifier Overloads If the above procedure is followed carefully no overloads should occur durin...

Page 56: ...meter of each generator can ad just the output at f O Therefore the two PARALLAX controls are interdependent Note also that there is no breakpoint at X O The first breakpoint occurs at X 1 in the Plus...

Page 57: ...cedure described below must be followed if precise switching levels are desired 2 Adjustment of Voltage Switching Level To obtain a precise voltage switching level say 5 volts proceed as follows Refer...

Page 58: ...I IN I 10K IN 2 0 SIMPLIFIED DIAGRAM IOV g A 5V IN I A o IOV CI IN2 VM 2 10 VOLT A RANGE A o Q b CIRCUIT FOR SETTING VOLTAGE SWITCHING LEVEL Figure 23 Rela Comparator Simplified Diagrams and Setup Pat...

Page 59: ...Figure 24 40 538 Electronic Comparator Unit ElEC COMP 40 538 49...

Page 60: ...t is applied to the unlatch terminal the analog in put voltages regain control of the comparator The binary ZERO applied to the un latch terminal overrides the binary ONE at the latch terminal so that...

Page 61: ...1 10 Afv LTH UNLTH r B o DIGITAL CONTROL BUFFER I e I COMPARATOR BISTABLE o I I I L_B 0 ___ J SJ COMPARATOR AMPLIFIER Fl gure 25 Comparator Unit Functional Block Diagram 51...

Page 62: ...52 DIGITAL INPUT 1 r I 10 I I I I I I I B CONTROL 10 Rin Rfb I I I I I L ___________________ J o Figure 26 Electronic Switch Unit Functional Block Diagram OUT...

Page 63: ...The CALIBRATE VERNIER permits continuous coverage between the fixed compute times and can increase the selected compute time by a factor of 2 5 2 A timing Unit that is located in the rear of the comp...

Page 64: ...E MILLISEC switch must be placed in the OFF po sition so that the relays in the Integrator Networks can ground the summing junctions If this is not done loading errors will cause the attenuators to be...

Page 65: ...M See 36 082 REP OP TIMING UNIT Note X INPUT TO 34 035 XDfI REP OP TIMING UNIT NOTE This jumper is required for operation of the 340035 Rep Op Display Unit in any mode other than CROSS PLOT or when an...

Page 66: ...NG AMPLIFIER SUMMING AMPLIFIER INTEGRATING AMPLI FIER ATTENUATOR LOWER END GROUNDED ATTENUATOR UNGROUNDED 0 FUNCTION SWITCH o A 1 SOLID STATE DIODE J V r FIXED RESISTOR t I CAPACITOR Y INPUT OF XY PLO...

Page 67: ...TYPE OF UNIT X 2 VDFG ETC I X ANALOG i INPUTS Y r r 1 I l J DIGITAL OUTPUTS o UN LTH LTH J DIGITAL INPUTS LOGIC DIGITAL 1 INPUT GATE JUNCTION ANALOG INAA INPUT OUT QUARTER SQUARE MULTIPLIER NOTE X MU...

Page 68: ...LIERS e APPENDIX II COMPUTER SYMBOL e1 e e IO __ e Ioe O le PATCHING e a w e e SJ e e 10 10 fD IOe e SJ e 1 1I O le 10 10 DUAL DC AMPL 6 712 COMMENTS STANDARD CIRCUIT lOOK INPUT IMPEDANCE 10K INPUT IM...

Page 69: ...N MULTI PLIERS CONTI NUEO COMPUTER SYMBOL e 2e OR eL 2e e e ke e ke 10 PATCHING e DUAL DC AMPL 6 712 SJ e I 10 1 e II II ATTEN e DUAL DC AMPL 6 712 2e e 2 m oo ke ke COMMENTS GAIN OF 2 GAIN OF 1 2 ke...

Page 70: ...CONTINUED ADDITION SUBTRACTION e e e COMPUTER SYMBOL 2 ke 2 ke ke I k PATCHING e e _e I e2 r 1 Ii 10 e3 4lf t 10 DUAL DC AMPL 6 712 COMMENTS 2ke FOR 0 k 1 ke FOR 1 k TYPICAL SUl i MATION CIRCUIT TYPI...

Page 71: ...ET 12 1116 REMAINDER OF PATCHING AS REQUIRED DUALINT NET 12 1116 REMAINDER OF PATCHING AS REQUIRED COMMENTS BASIC INTE GRATOR CIR CUlT TYP ICAL SUM MING INTEGRA TOR CIRCUIT INTEGRATOR IS IN RESET WH E...

Page 72: ...M PUTER IN OPER ATE INTEGRATOR AS REQUIRED IN OPERATE WHEN AS REQUIRED AS REQUIRED REMAINDER OF PATCHING AS REQUIRED DUALINT NET 12 1115 REMAINDER OF PATCHING AS REQUIRED REMAINDER OF PATCHING AS REQU...

Page 73: ...X Y Y IOV X IOV IOV Y IOV Y IOV X IOV Y O Y IOV X X O X IOV x X _ XV 10 lOX XY _x2 10 PATCHING x IO x 0 S _____ IlroJ Y B MULT REF 7 04 x _ Y Y X x X eo XV 10 eo eo eo o t L t W MULT REF 7 04 COMMENT...

Page 74: ...ATI 8 CIRCUIT OESCR I PTION QUARTER SQUARE MULTIPLIER x COMPUTER SYMBOL x PATCHING eo COMMENTS POSITIVE INPUT ft NEGATIVE INPUT...

Page 75: ...OL 01 x OSXS IO IOSXSO IOSXS IO 2 X IOSXSO x2 10 xlxl 10 ViOX PATCHING tiN X j s o X2 DFG x 5 B o a fiN o _ t B tiN 4 5 4 x X2 0 X2 10 xlxl 0 COMMENTS X2 POSITIVE INPUT X2 NEGATIVE INPUT X2 BI POLAR I...

Page 76: ...COMPUTER SYMBOL 0 X 10 IO X IO IOSX 10 X y2 10 X x x x Y PATCHING IN s _ O _ r IN s__ v1Ox COMMENTS jX POSITIVE INPUT i x DIODE VOLTAGE DROP x2 BI POLAR INPUT POSITIVE OUTPUT x2 81 POLAR INPUT NEGATI...

Page 77: ...IRCUITS I X ioANTILOGIO 151 SI LOG X IN 0 1 X lANTILOG I I 10 10 5 PATCH ING X 2LN lOX x 5 LOG IO lOX 2LN 10 0 0 IN X 0 IN __ 1 ANTILOG I I lO 10 5 COMMENTS LOG X POSITIVE INPUT BASE 10 AND NATURAL LO...

Page 78: ...2 LOG X IN X 4343 CIRCUITS CONTINUED 10 LOG 10 lOA AII 12 C C A lOX ex Ae PATCHING x x INo__ _ o o 16ANTILOGe I j 10 X IN 10 o II o COMMENTS ANTILOG X NEGATIVE INPUT NATURAL BASE ANTILOG X POSITIVE IN...

Page 79: ...REAKPOINT UNITS X COMPUTER SYMBOL r l B VDFG 8 2 2 05X5 10 IO X O IO X IO f f X O f X X X X 16 308 OR 16 310 16 309 OR 16 311 PATCHING COMMENTS POSITIVE X NEGATIVE X e t f X BI POLAR X POSITIVE X f X...

Page 80: ...CIRCUIT DESCR IPTtON RELAY COMPARATOR 6 143 COMPUTER SYMBOL Ej Ei 10 10 Ej 10 10 r _ A 10 0 Eo 10 A 10 COMMENTS Eo 3II Ei Eo ABSOLUTE VALUE DEAD ZONE Ei BACKLASH 2A AIl 15...

Page 81: ...CIRCUIT DESCRIPTION RELAY COMPARATOR 6 143 CONTINUED AII 16 COMPUTER SYMBOL CI Eo Ej 10 10 Ej C2 Eo A 10 10 10 10 0 A 0 10 EO CI Ej 10 10 Ei A 10 10 10 COMMENTS Eo Eo LIMITS Eo BANG BANG...

Page 82: ...CIRCUIT OESCRI PTION ELECTRONIC COMPARATOR 40 538 x Y DIG DIG I COMPUTER SYM B o UN LTH LTH COMPARATOR DIGITAL GATE I B UN LTH LTH...

Page 83: ...ER NPUT X Y PATCHING ELECTRONIC COMPARATOR UNLATCH INPUTCBINARY o GRO ELECTRONIC COMPARATOR BINARY I OUTPUT 5V ELECTRONIC SWITCH 2 DIGITAL INPUT DIRECT ANALOG INPUT SWITCH 2 UNITY GAIN ANALOG INPUT SW...

Page 84: ...B J o 0 x Y lOGIC IN PUT o NOTE THESE DIAGRAMS ONLY SHOW THE SWITCH PATCHING FEEDBACK MUST BE PROVIDED AROUND THE AMPLIFIER OR OVERLOAD WILL OCCUR WHEN THE SWITCH STOPS TRANSMIT TING B o WHEN THE lOGI...

Page 85: ...ATCHING AS REQUIRED REMAINDER OF PATCHING AS REQUIRED COMMENTS SELF LATCHING CIR CUIT WHEN X Y 0 DIG 1 TERMINAL GOES TO 5 VOL TS OUTPUT REMAINS IN THIS STATE UNTIL MANU AllY RESET WITH FUNCTION SWITCH...

Page 86: ...g transfer functions A more complete llsting may be round in Jackson A S Analog Computation MCGrall 9Hill B ook Com Inc New York 1960 BODE PLOT TRANSFER TIME FUNCTION CONSTANTS B E E I I V 0 0 A GAINS...

Page 87: ...admittance and component values tor some usetul networks tor simulating transfer tunctions A more extensive listing I1lB y be round in Jackson A S IIAnalog Computation and Fifer s Analog Computationu...

Page 88: ...TTANCE 1 1 pT A pSI e 1 1 1 pT A 1 pSI e 1 1 1 pSI A 1 pT C 1 1 per A 1 pr e 1 l1 pGr A 1 pT e 1 1 1 pTl 1 pT3 A 1 pT2 NETWORK R2 A R1 R2 c R R T R2C R1 A R1 T R1 R2 C A 2ft1 R T R2 2 C 2 2R e 2 2R2 R...

Page 89: ...ublishing Company Inc Reading Massachusetts 1959 Karplus W J Analog Simulation McGraw Hill Book Company Inc New York 1958 Mathews M V and Seifert W W Transfer Function Synthesis with Computer Amplifie...

Page 90: ...puting in the Chemical and Petroleum Industries Past and Present Williams T J Industrial and Engineering Chemistry Vol 50 1958 p 1631 Application of General Purpose Analog Computer to Unsteady State D...

Page 91: ...l Engineers Vol 76 Pt II No 31 July 1957 pp 105 109 discussion pp 109 110 Jet Engine Simulation for Engine Control Development Work Sherrard E S Proceedings of the National Simulation Council presente...

Page 92: ...and Development Command WADD Technical Note 59 344 Project 1365 Wright Patterson Air Force Base Ohio July 1960 ASTIA No AD 246 530 Simulation of Military Vehicle Suspension Systems Sattinger I J and...

Page 93: ...is A 1958 mE WESCON Convention Record Vo1 2 pt 1 presented at Los Ange les August 19 22 1958 pp 70 85 and Microwave Applications Seminar Electronic Associates Inc Computation Center at Los Angeles Oct...

Page 94: ...alog Computer Reihing J V Jr Proceedings of the Western Joint Computer Conference presented at San Francisco March 3 5 1959 p 341 Analog Representation of Heat Exchange Application to the Simulation o...

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