EACA EG 3014 Technical Manual Download | Manualshive

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Summary of Contents for EG 3014

Page 1: ...EG 301 4 EG 302 EXPANSION TECHNICAL MANUAL...

Page 2: ...o it The manual can be regarded as a reference or a reminder to the experienced technical people It is expected that the reader should have the basic knowledge of digital electronics in order to make...

Page 3: ...E _ _ _ _ _ __ _ _ _ 16 2 1 UART __ _____ ____ 16 2 1 1 Control Bits _ _ _ _ _ _ _ _ _ _ 16 2 1 2 Clock __ ________ 16 2 2 Baud Rate Generator _ _ _ _ _ _ __ _ _ _ 17 2 3 Address Decode _ ___ _ _ __ _...

Page 4: ...ctors between the S 100 Bus Interface Board and the Mother Board _ _ _ 26 4 7 2 1 50 pin PCB Solder to board Connector _ _ _ _ 26 4 7 2 2 34 pin PCB Solder to board Connector _ 27 4 7 3 Pin Assignment...

Page 5: ...disk controller and interface and parallel printer interface There are optional interface boards that can be added to the Expander They are the RS 232 C interface and S 100 Bus interface The circuits...

Page 6: ...further expansion 6 power supply and regulators These functional blocks are illustrated in Fig 1 1 Fig 1 1 ZJ CQ c o n C Q X CJ LU Address Y Buffer Data Buffer Control Status Buffer Address Decode Mem...

Page 7: ...enable signals of a serial port F8H or F9H and of a parallel printer port of FDH 1 2 MEMORY RAM This part consists of dynamic RAM chips address multiplexer data buffers 74LS244 and control timing logi...

Page 8: ...or a real time clock occurs every 25 msec This 40 Hz interrupt signal is obtained from a series of dividers Z54 Z50 Z45 and Z44 1 3 2 Drive Select In order to select a drive it is required to write a...

Page 9: ...ter Data Register Data Register 1 3 4 Data Separation 1 3 4 1 Internal Data Separator FD1771 provides an internal data separation by pulling HIGH the signals XTDS pin 25 and FDCLOCK pin 26 The raw REA...

Page 10: ...d as in Fig 1 3a Fig 1 3b shows the timings of the data separator Fig 1 3 EXTERNAL DATA SEPARATOR a Circuit FROM Z47 13 v READ DATA Z55 c Z59 1 r tf SEP DATA i SEP CLOCK Z59 9 C 13 Z55 R LI S Q 10 3 1...

Page 11: ...READ DATA which are negative going pulses pass through Z47 one shot Positive going pulses with width of about 200 nsec are obtained from output of Z47 pin 13 Z55 forms a data window and a clock windo...

Page 12: ...Side Select signal is derived from the Drive Select signals For instance jumpers in positions 2 and 4 at J5 are added When Side Select is HIGH the Side of diskette corresponding to DS1 and DS3 respect...

Page 13: ...line bit 7 of status lines This positive pulse is generated just after the data are clocked into the latch and inhibits further data transfer from the CPU to the printer before the printer sets the s...

Page 14: ...ATA IN ENABLE 9 BD6 DATA BIT 6 10 BD5 DATA BIT 5 11 BD0 DATA BIT 12 BD7 DATA BIT 7 13 BD2 DATA BIT 2 14 BD1 DATA BIT 1 15 BA2 H ADDRESS LINE 2 16 BD3 DATA BIT 3 17 BA0 H ADDRESS LINE0 18 BA1 H ADDRESS...

Page 15: ...48 RD L PROCESSOR READ CYCLE 49 GND 50 GND 1 5 2 Pin Assignment for the 20 pin Connector PIN SIGNAL ACTIVE LEVEL 1 BD5 2 BD4 3 BD7 4 BD6 5 BD1 6 BD0 7 BD3 8 BD2 9 BWR 10 BAO 11 BRD 12 SRESET 13 8MHz...

Page 16: ...Load Voltage Remark min max min max 8V 10 5V 11 5V 8V 9V F L 8V 1 2A 16V 20V 24V 15V 18V F L 16V 1 50mA 16V 20V 24V 15V 18V F L 16V 100mA There are three voltage regulators on the expander board IC re...

Page 17: ...ART The serial data format can be determined by properly setting the control bits This can be done by turning ON or OFF the dip switches SI S5 of DP1 2 1 1 Control Bits ON 0 and OFF 2 1 1 1 2 1 1 2 2...

Page 18: ...ADDRESS INPUT TO CPU OUTPUT TO INTERFACE SERIAL INPUT F8H DATA STATUS SERIAL OUTPUT F9H STATUS DATA SERIAL PRINTER FDH STATUS DATA The mode of operation can be chosen as below DP1 MODE S6 SZ S8 Serial...

Page 19: ...5 1 The pin assignment for the RS 232 C Bus is as follows PIN SIGNAL DESCRIPTION 1 PGND Protective Ground 2 TXD Transmit Data OUT 3 RXD Receive Data IN 4 RTS Request to send OUT ON peripheral to trans...

Page 20: ...T 6 DATA BIT 1 DATA BIT DATA BIT 3 DATA BIT 2 PROCESSOR WRITE ADDRESS LINE PROCESSOR READ SYSTEM RESET 8 MHz 50 DUTY CYCLE SERIAL PORT SELECT SEMI REGULATED PARALLEL PRINTER PORT SELECT REGULATED REGU...

Page 21: ...sity FM storage and the FD1791 controls the operation of double density MFM storage The pin out of FD1771 is similar to that of FD1791 Some exceptions are that FD1791 has two write precompensation out...

Page 22: ...ontains a delay circuit Z13 74LS74 and a multiplexer Z7 74LS153 Z7 is controlled by the signals EARLY and LATE from Z1 FD1791 3 6 DATA SEPARATOR Counter type data separator is employed for both single...

Page 23: ...SITY FM Q Z5 6 Z3 9 READ 26 6 DATA WINDOW Z3 II B Qa Z3 II Z3 I2 Z3 I3 Z3 I4 8yusec COUNT UP Whenever the clock pulse of a bit cell is encountered Z3 9 becomes LOW going and Z3 will count up from the...

Page 24: ...applied to the READ CLOCK input of FD1791 The timing diagram of generating the window is shown in Fig 3 3 Fig 3 3 DATA SEPARATION DOUBLE DENSITY MFM BIT CELLS Q Z5 6 READ DATA Z6 6 WINDOW Z3 11 Qd Qc...

Page 25: ...ines from the expander are split into 8 DATA IN lines and 8 DATA OUT lines These lines are buffered by Z8 and Z9 74LS244 4 4 CONTROL STATUS LINES The control status lines of S 100 bus are generated fr...

Page 26: ...d 8V 16V and 16V dc supply lines are required in S 100 Bus TheS 100 Bus interface board contains a voltage regulator Z1 7805 Z1 regulates 8V supply into 5V for the TTL logic IC s of the S 100 Bus inte...

Page 27: ...and the Mother Board Refer to the component layout diagram 4 7 2 1 50 pin PCB Solder to board Connector PIN SIGNAL PIN 1 VM 26 2 GND 27 3 16V 28 4 5V 29 5 6 VI2 VI 30 31 7 16V 32 8 8V 33 9 VI6 34 10...

Page 28: ...iiption of these signals refers to Section 4 7 3 Ha v m mt for the S 100 Bus Connector on the Mother Board itSflgfrs e component layout diagram ACTIVE SIGNAL LEVEL DESCRIPTION semi regulated max 2A se...

Page 29: ...ynamic Ram refreshing signal Address lines and data output disable Master clock 1 7 MHz Processor HOLD acknowledge Address line 5 Address line 4 Address line 3 Address line 15 Address line 12 Address...

Page 30: ...Bus hold control signal LO C Reset control signal L Processor write control signal H Processor read control signal H Address line H Address line 1 H Address line 2 H Address line 6 H Address line 7 H...

Page 31: ...5 COMPONENT LAYOUT DIAGRAM EG 3014 EG 3020 EG 3021 and EG3022 30...

Page 32: ...I iT oo CO O I 89E eez 89 CO a a a SSI fez EC I 89C SEZ o o o o 1 1 0 A CM CO 0 a 6Ld 9SI tez 00 2G2 8td Zld et06 n ozo 6 L 62Z frfrZ oez i i l CM CO w a a a 08 zzz frfrZ 82Z oe egz frfrZ frgZ frO SgZ...

Page 33: ...o CM O CM to 0 r Q r CVJ t N N r r CM O N ON o O O M SHI II CM o Hh O o Hh DP1 E o M O N a cc LU o I CM CO CM CO cc o CM O CO o LU CO 00 J O CO J 00 T CO T o CO T o CM 00 v N N M r I 32...

Page 34: ...T H Kb H 1 R7 Z12 04 Z4 161 Z5 74c c 3 R 4C5 C6 _L T R1 h Z10 02 Z3 161 Z6 74 c 4 C7 Zl 1791 c Z7 153 Z2 1771 c Z8 157 I h R8 R3 C2 _ Z9 30 Z11 02 j C8 1 EG 3021 LAYOUT DIAGRAM EG 3021 DOUBLE DENSITY...

Page 35: ...CN 1 4 1 so 47 CN 2 4 1 C14 r o i 50 100 P 1 1 51 50 100 P 2 si 680 J 0 1 O C11 680 680 660 10U vC R3 RIO 1 7kvo 1 I 3 av 9 cz I 220 I I o CJ2 IZ C 1 A 220 I i 1 220 C13 k 220 o MOTHER BOARD EG3022 S...

Page 36: ...6 SCHEMATICS EG3014 EG3020 EG3021 and EG3022 35...

Page 37: ...o K en e j I n m r o n m r at lO V M D Q D D 8 s II QQQQQgnnnnnnnnno r n w N pjoj N n w m n n rg As A CO OB9 I OCC O M V 1 WW r o oo u m r n cv cy oj cm pj em oj W t DO0D00QD0000D0D0 CsJ CO 9 g Q Q o...

Page 38: ...16V Q3 00 C6 33WV C2 CA C17 C22 o UF CS2 M Sft 33UMV 0 5V 4 KU WV BRD O Z11 4116 o 5V 0 5V H Ofl2V OGND O SV 0 5V 0 12V O GND LS244 LSOO EG3014 EXPANDER sheet 2 37...

Page 39: ...CO D 38...

Page 40: ...53 LS244 or 11 15 Z43 LS175 7 4 13 Z49 LS175 12 52 5V 5V 5V 0 PRINTER BUS v C73 02U T 2 R46 IOOK 5V 0 Z57 o LS123 U 5V O EG 3014 EXPANDER sheet 4 30 21 BUSY 23 CZIOUT PAPER 25 CHUNIT SEL izr gnd 2 4 6...

Page 41: ...OH2V B a 3 CH2 TXD CD3 RXD CH7 SGND C31 PGND CD8 CD CD6 DSR as crs CZI20DTR CZI4 RTS i RS232C BUS EG3020 RS 232 C INTERFACE 4G...

Page 42: ...We o DAL 3 e WS O JT TE R3 10 0 W C2 Ji Z9 30 Ji _li 10 c Z8 3 7 Yl Y2 Y3 Y4 STEP 16 DIRE TO FLOPPY INTERFACE J2_ WO WG B A R6 390 I Yl 7 9 1 ff lDOoT T C4 2 H Z7 153 Z10 1 Qir Jl Z6 74 CK R2 7K Mf o...

Page 43: ...EXPANDER S1Q0 BUS EXPANDER S100 BUS MREG OOCK B PHANTOM PHOLO i PHANlTO EG3022 S 100 BUS INTERFACE 42...

Page 44: ...23 A14 25 NC 27 A13 29 A12 31 PINT 33 NC 35 PHANTOM 37 PWAIT 39 PHOLD 41 RD 43 MREQ 45 M1 47 RFSH 49 GND 2 GND 4 A6 6 A4 8 A3 10 AO 12 D2 14 D1 16 D3 18 D6 20 D4 22 A8 24 A9 26 A10 28 A11 30 PHI 32 NC...

Page 45: ...EACA INTERNATIONAL LTD 1 3 Chong Yip Street Eaca Industrial Building Kwun Tong Kowloon HONG KONG Telex 54035 ECHK HX Cable ECHUNG H K Tels 3 896323 8 Lines COPYRIGHT BY EACA 1981 ALL RIGHTS RESERVED...

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