TSEV8388B - Evaluation Board User Guide
4-1
0973D–BDC–02/09
e2v semiconductors SAS 2009
Section 4
Application Information
4.1
Introduction
For this section, refer also to the product Specification application notes (TS8388BGL
Datasheet). More particularly, refer to sections related to single-ended and differential
input configurations.
4.2
Analog Inputs
The analog inputs can be entered in differential or single-ended mode without any high
speed performance degradation.
The board digitizes single-ended signals by choosing either input and leaving the other
input open, as the latter is on-board 50
Ω
terminated. The nominal In-phase inputs are
V
IN
(See Section 3).
4.3
Clock Inputs
The clock inputs can be entered in differential or single-ended mode without any high
speed performance degradation. Moreover, the clock input common mode may be 0V,
or -1.3V if ECL input format is used for the clock inputs.
As for the analog input, either clock input can be chosen, leaving the other input open,
as both clock inputs are on-board 50
Ω
terminated. The nominal in-phase clock input is
CLK (See Section 3).
4.4
Setting the
Digital Output
Data Format
For this section, refer to the Evaluation Board Electrical schematic and to the compo-
nents placement document (respectively Figure 6-1 and Figure 6-7).
Refer also to the TS8388B specification pages about digital output coding.
The TS8388B delivers data in natural binary code or in Gray code. If the “GORB” input
is left floating or tied to V
CC
the data format selected will be natural binary, if this input is
tied to ground the data will follow Gray code.
Use the jumper denoted ST2 for selecting the output data port format:
If ST2 is left floating or tied to V
CC
, the data output format is true Binary,
If ST2 is tied to GND, the data outputs are in Gray format.
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