e2v EV10AS150A, User Manual, Page: 9 / 51

Hardware Description
EV10AS150A-EB User Guide 2-3
0977B–BDC–10/09 e2v semiconductors SAS 2009
Figure 2-1. Figure 2-1.Board Layout for the Differential Analog and Clock Inputs
Figure 2-2. Differential Analog Inputs Implementation
Figure 2-3. Differential Clock Inputs Implementation
2.3 Digital Output
The digital output lines were designed with the following recommendations:
„
50
Ω
lines matched to ±0.5 mm (in length) between signal of the same differential pair
„
80 mm max line length
„
±1 mm line length difference between signals of two ports
„
±1.5 mm max line length difference between all signals
„
770 µm pitch between the differential traces
„
370 µm line width
„
40 µm thickness
200 µ m
RO4003
400 µm
400 µm
870 µm
µ 1270 m
e = 40 µm
Ground plane
VIN (H27)
VINN (J27)
VIN
VINN
100 pF
100 pF
EV10AS150A
100 pF
CLK
CLKN
CLK (W23)
CLKN (RW24)
100 pF
EV10AS150A