e2v EV10AS150A, User Manual, Page: 8 / 51

Hardware Description
2-2 EV10AS150A-EB User Guide
0977B–BDC–10/09
e2v semiconductors SAS 2009
The board is 1.6 mm thick.
The clock, analog input, reset and digital data output signals occupy the top metal layer
while the ADC and DMUX functions are located both on the top.
The ground planes occupy layer 3, 13 and 15 (partly).
Layer 5, 7, 9 and 11 are dedicated to the power supplies.
2.2 Analog
Inputs/Clock
Input
The differential active inputs (Clock, Analog) are provided by SMA connectors.
Reference: VITELEC 142-0701-8511
Special care was taken for the routing of the analog input and clock input signals for
optimum performance in the high frequency domain:
„
50
Ω
lines matched to ±0.1 mm (in length) between V
IN
and V
INN
and between CLK
and CLKN
„
50 mm max line length
„
1.27 mm pitch between the differential traces
„
400 µm line width
„
40 µm thickness
„
850 µm diameter hole in the ground layer below the V
IN
, V
INN
, CLK and CLKN ball
footprints
Layer 9
Copper layer
Copper thickness = 35 µm
Power planes = V
CCA3
Layer 10
FR4 HTG/dielectric layer Layer thickness = 200 µm
Layer 11
Copper layer
Copper thickness = 35 µm
Power planes = V
PLUSD
Layer 12
FR4 HTG/dielectric layer Layer thickness = 170 µm
Layer 13
Copper layer
Copper thickness = 35 µm
Ground plane = reference plane (identical to layer 3)
Layer 14
FR4 HTG/dielectric layer Layer thickness = 200 µm
Layer 15
Copper layer
Copper thickness = 40 µm
DC signals traces and Serial Interface (AVR) signals
Ground plane
Table 2-1. Board Layer Thickness Profile (Continued)