CIRCUIT DESCRIPTION
6-4
September 1994
Part No. 001-2008-300
Figure 6-3 SYNTHESIZER BLOCK DIAGRAM
(OPEN-DRAIN OUTPUT)
15
OUTPUT B
DATA OUT
24 BITS
A REGISTER
INPUT AMP
PRESCALER
64/65
in
f
in
f
10
11
LOGIC
MODULUS
CONTROL
N COUNTER
12-STAGE
A COUNTER
6-STAGE
CONTROL
INTERNAL
POR
LOGIC
STANDBY
8 BITS
C REGISTER
ENABLE
17
19
DATA IN
CLOCK
18
LOGIC
CONTROL
AND
REGISTER
SHIFT
16 BITS
R REGISTER
DOUBLE-BUFFERED
13-STAGE R COUNTER
DIVIDER
4-STAGE
OSC OR
out
REF
20
in
REF
1
OR (UP)
OV (DOWN)
16
OUTPUT A
LOGIC
SELECT
PORT
V
f
R
f
V
R
2
LOCK DETECT
AND CONTROL
LD
f
f
V
R
f
f
PHASE/FREQUENCY
DETECTOR B
AND CONTROL
PHASE/FREQUENCY
AND CONTROL
DETECTOR A
V
R
f
f
3
4
8
6
Rx
PDout
TEST 2
TEST 1
13
9
Data is loaded into U209 serially on the Data
input port U209, pin 19. Data is clocked into the shift
registers a bit at a time by a low to high transition on
the Clock input port U209, pin 18. The Clock pulses
come from the TPI via the IAC to J201, pin 18. The
bit pattern is 8-bits long to access the C register, 16-
bits to access the first buffer of the R register, or 24-
bits to access the A register.
The values in the C, R, and A registers do not
change during shifting because the transfer of data to
the registers is controlled by ENABLE. The 13 LSBs
of the R register are double-buffered. Data is latched
into the first buffer on a 16-bit transfer. The second
buffer of the R register contains the 13-bits for the R
counter. This second buffer is loaded with the con-
tents of the first buffer when the A register is loaded (a
24-bit transfer). This allows presenting new values to
the R, A and N counters simultaneously.
The other input signal (f
V
) is from the VCO fre-
quency divided down by the synthesizer "N" and "A"
counters to 12.5 kHz. These counters are programmed
through the synthesizer data line on J201, pin 20.
Each channel is programmed by a divide number so
that the phase detector input (f
V
) is identical to the ref-
erence frequency (f
R
) when the VCO is locked on the
correct frequency.
The synthesizer contains the R (reference), N,
and A counters, phase and lock detectors and counter
programming circuitry.
Frequencies are selected by programming the
three counters in U209 to divide by assigned num-
bers. The programming of these counters is per-
formed by circuitry in the Third Party Interface (TPI),
which is buffered and latched through the Interface
Alarm Card (IAC) and fed into the synthesizer on
J201, pin 20 to Data input port U209, pin 19.
