E.F. Johnson Company 5100 ES, Service Manual

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5-6 5100 ES Series Portable Radio Service Manual January 2007
Circuit Description
KHz bandwidth. Shields installed around the crystal filter provide sufficient isolation to
meet the second image response specifications and minimize noise pickup by the
impedance-matching inductors (L1, L2, L3, L4 and L7.)
A transistor IF amplifier (Q1 and supporting circuitry) is required to boost the signal
strength, thereby reducing the overall noise figure. The noise figure, signal gain, intercept
point, and power consumption are optimized in this design. An additional two-pole 64.455
MHz crystal filter (U25) is used to increase the adjacent channel rejection. An LC circuit
provides the required impedance matching between the output of the IF filter and the input
of the backend chip (U11.)
5.2.1.6 Back End IC
An Analog Devices AD9864 IF Digitizing Subsystem IC (U11) provides a variety of
functions for the receiver as follows:
Second Local Oscillator - A varactor-tuned transistor (Q2) oscillator is phase-locked to
a fixed frequency of 62.355 MHz for converting the first IF of 64.455 MHz to a second
IF frequency of 2.1 MHz. Phase Locked Loop circuitry inside of the AD9864 operates
with a phase-detector frequency of 15 kHz.
Second Conversion Mixer and Filtering - A mixer inside the AD9864 converts from the
first IF of 64.455 MHz to the second IF of 2.1 MHz. External filters (L29 and L30)
provide IF bandpass filtering. Additional filtering is provided by the inherent operation
of the sigma-delta analog/digital converters.
Gain Control - This device provides up to 12 dB of AGC range via a combination of
analog and digital controls. Additionally, there is a 16 dB attenuator in the front end.
The optimum settings are controlled by the host microprocessor.
Analog / Digital Conversion and Processing - Sigma-delta converters provide I and Q
sampling directly from the second IF frequency. The resulting digital words are first
filtered by internal programmable FIR filters and then clocked out of the AD9864 via a
serial data bus using a programmable data rate.
5.2.2 Synthesizer
5.2.2.1 PLL IC
A CX72301 sigma-delta modulated PLL (U29) forms the basis of the main synthesizer
that is used for both receive and transmit modes. This PLL chip provides good phase noise
capabilities to reduce adjacent channel interference and quick switching between the
receive and transmit modes.
In receive mode the PLL is programmed for a local oscillator frequency that is 64.455
MHz away from the receive frequency. In transmit mode the PLL is programmed directly
for the transmit frequency.