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Dynatem CPU-111-10, User Manual

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Appendix B 

– BIOS & Setup 

Dynatem 

CPU-111-10 - Intel Xeon Quad-Core 6U VPX SBC – User’s Manual 

33 

Note: PATA cable autodetection sometimes fails with older drives, so 40-pin is the default, to ensure data integrity. 
For higher performance, you should change this setting to 80-pin or AUTO if an 80-pin cable is installed.

 

 
B.7 

POST Setup Menu 

 

The POST menu is used to configure POST. This menu is shown in the following figure (scrolled down more so the 
full set of options can be seen.) Be sure to review the Features menu, where additional items can be configured, such 
as the Splash Screen and BIOS initiatives. 
 

 

 
The figure below shows the same menu, scrolled down so that the remainder of its fields may be 
viewed. 

Summary of Contents for CPU-111-10

Page 1: ...USER MANUAL CPU 111 10 VPQ Intel Xeon Quad Core 6U VPX Single Board Computer CPU 111 10_User_Manual_d0 1 doc Updated 25mar2013 ...

Page 2: ...CPU 111 10 User s Manual Rev Draft 0 1 March 25 2013 Dynatem 23263 Madero Suite C Mission Viejo CA 92691 Phone 949 855 3235 Fax 949 770 3481 www dynatem com ...

Page 3: ...9 3 3 5 Silicon Motion SM750 Graphics Controller 9 3 4 10 GIGABIT ETHERNET ARCHITECTURE 10 3 4 1 Fulcrum FM3224 Switch 10 3 4 2 Intel 82599 Dual 10GB Ethernet 11 3 4 3 SFP Interface AEL2009 12 3 4 4 VPX 10Gb Ethernet I O 12 3 4 5 XMC 10GbE I O 13 3 5 VPX GENERAL PURPOSE I O 13 3 6 CLOCKING 13 3 7 RESET STRUCTURE 14 3 8 SMBUS ARCHITECTURE 15 3 9 BOARD POWER 16 3 10 REAR TRANSITION MODULE 17 4 INSTA...

Page 4: ...3 B 8 PNP SETUP MENU 36 B 9 SUPER I O SIO SETUP MENU 37 B 10 FEATURES SETUP MENU 38 B 11 FIRMBASE SETUP MENU 39 B 12 MISCELLANEOUS SETUP MENU 41 C POWER AND ENVIRONMENTAL REQUIREMENTS 43 D RTM REAR PLUG IN I O EXPANSION MODULE FOR THE CPU 111 10 44 D 1 RTM VPX PIN OUTS 44 D 2 CPU 111 10 REAR TRANSITION MODULE PIN OUTS 46 D 3 REAR PANEL CONNECTOR PIN OUTS 46 ...

Page 5: ...ND INDICATORS 20 List of Tables TABLE 1 VPX P0 CONNECTOR PIN OUTS 21 TABLE 2 VPX P1 CONNECTOR PIN OUTS 21 TABLE 3 VPX P2 CONNECTOR PIN OUTS 22 TABLE 4 VPX P3 CONNECTOR PIN OUTS 22 TABLE 5 VPX P4 CONNECTOR PIN OUTS 23 TABLE 6 VPX P5 CONNECTOR PIN OUTS 23 TABLE 7 VPX P6 CONNECTOR PIN OUTS 24 TABLE 8 PCI X MEZZANINE CARD CONNECTOR PIN OUTS 24 TABLE 9 XMC CONNECTOR PIN OUTS 25 TABLE 10 SFP CONNECTOR P...

Page 6: ... O expansion including 10G XAUI lanes from each XMC card to the 10G switched fabric Features of the CPU 111 10 include OPENVPX COMPATIBLE Rugged Single Slot 6U Single Board Computer compatible with VITA 65 OpenVPX Payload Module Profile MOD6 PAY 4F2T 12 2 2 4 4x 10GBase BX4 Fat Pipes and 2x 1000Base T Thin Pipes HIGH PERFORMANCE x86 CPU 4 Core Intel Xeon L5408 Processor 2 13 GHz with 4GB of DDR2 R...

Page 7: ......

Page 8: ...eet Doc No 318378 003U July 2008 Intel 5100 Memory Controller Hub Chipset for Communications Embedded and Storage Applications Thermal Mechanical Design Guide Doc No 318676 003US July 2008 Intel Xeon Processor 5000 Sequence with Intel 5100 Memory Controller Hub Chipset for Communications Embedded and Storage Applications Platform Design Guide Doc No 352108 2 3 April 2009 Intel I O Controller Hub 9...

Page 9: ... Sec 5 3GB Sec 5 3GB Sec 2GB Sec 2 5MB Sec 60MB Sec x4 XAUI 6 Intel 82599EB Dual 10GigE Niantic XAUI 9 XAUI 10 10GigE x2 XAUI 0 XAUI 8 10GigE x1 1GigE x2 Dual PMC XMC Sites 2GB Sec SFP FRONT PANEL COPPER FIBER INTERFACE 1 25GB Sec x2 125MB Sec x2 1 25GB Sec x1 10GigE x1 1 25GB Sec x1 XAUI 11 SFI Gen2 PCIe x8 P 0 5 P 0 4 STN 0 P 0 STN 1 P 5 STN 2 P 9 STN 2 P 8 PE6 PE7 PE4 PE5 PE2 PE3 PE0 P 0 P 1 P ...

Page 10: ...Chapter 3 Hardware Description Dynatem CPU 111 10 Intel Xeon Quad Core 6U VPX SBC User s Manual 5 Specifications ...

Page 11: ... XMC sites 8 lanes each and a PLX PEX8624PCIe Switch 8 lanes for further PCI Express distribution The MCH supports up to 4 GBytes of DDR2 SDRAM running at up to 1066 MHz double data rate speeds MCH features include Intel 5100 MCH with 1066 1333 MHz Front Side Bus 4GB DDR2 ECC SDRAM at 533 667 MHz 1066 MHz DDR Two x8 PCI Express Ports to XMC Sites One x8 PCI Express Port to PEX8624 Gen 2 PCIe Switc...

Page 12: ...Chapter 3 Hardware Description Dynatem CPU 111 10 Intel Xeon Quad Core 6U VPX SBC User s Manual 7 ...

Page 13: ... two x4 PCIe links to two IDT Tsi384 PCIe to PCI X Bridges providing a PCI X interface for each PMC site The switch also supports a x8 link to an Intel 82599 Dual 10Gb Ethernet Controller providing a high speed connection in the on board 10GB Ethernet switch fabric The ICH9R has two PCIe ports One x4 port is connected to an Intel 82571 Dual 1Gb Ethernet Controller to support 1000BASE T backplane c...

Page 14: ...l 82571 Gigabit Ethernet Controller is a single component containing two fully integrated Gigabit Ethernet Media Access Controllers and physical layer ports Both ports contain a SerDes to support Gigabit backplane applications The 82571 provides high performance and low memory latency using a x4 PCI Express link to the ICH9R I O Hub Complies with 1Gb Sec Ethernet 802 3ap x4 PCI Express interface t...

Page 15: ... Ethernet Architecture 3 4 1 Fulcrum FM3224 Switch The FM3224 10GbE Switch is the heart of the CPU 111 10 SBC Using 10Gb Ethernet it connects the backplane to the CPU XMC Modules and front panel SFP Fiber Optic I O modules not included with the CPU 111 10 The FM3224 is a fully integrated single chip wire speed 10G Ethernet switch In addition to enhanced layer 2 functionality the FM3224 layer 3 cap...

Page 16: ...eed CPU path into the switch fabric for both data and switch management The interface to the switch consists of dual channel XAUI IEEE 802 3ae The 82599 connects via x8 Gen2 PCIe to the PEX8624 PCIe switch and from there to the CPU As previously mentioned the 82599 also supports IEEE 1588 precision time protocol PTP by time stamping in coming and out going data packets Figure 5 82599 Block Diagram...

Page 17: ... backplane The CPU 111 10 complies with the VITA 46 OpenVPX standard for profile MOD6 PAY 4F2T 12 2 2 5 This profile covers the four 10GbE channels on VPX connector P1 The remaining three 10GbE channels connect to P2 P4 and P5 10GbE Port 23 KEY KEY SE P0 J0 S E Data Plane 4 Fat Pipes 4 10GBASE KX4 P2 OpenVPX Profile MOD6 PAY 4F2T 12 2 2 5 Control Plane Two Thin Pipes 2 1000BASE T 10GbE Port 12 10G...

Page 18: ...e CPU and PCIe peripherals It also generates 48MHz 33MHz and 14MHz clocks used throughout the CPU 111 10 Clocks for DDR SDRAM are generated by the MCH Separate 312 5MHz and 125MHz oscillators provide clocks to the FM3224 10GbE Switch DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM CK505 CLOCK GENERATOR CPU_ITP MCH_ITP DB400 PEX8624 Tsi384 1 Tsi384 2 82599 XMC 1 XMC ...

Page 19: ...PU LPC HDR FWH FM3224 AEL2005 82571 SSD DDR REG MCH_ITP CPU_ITP DDR REG MCH PMC 1 PMC 2 ICH9R ispPOWR 1220A CPU CORE SUPPLY VPX P1 VPX P0 DUAL DBNCR FET SWITCH SYSCON BP_SYSRST RESET SWITCH VRM_PWRGD BP_SYSRST PB_SYSRST ICH_CPU_PWRGD PLTRST PLTRST1 PLTRST2 RSMRST SYS_PWRGD SYS_PWRGD_3V3 CPU_PWRGD ICH_PWRBTN PLTRST CPURST PCI_RST1 PCI_RST2 Figure 8 Reset Structure When all non core supplies are up ...

Page 20: ...enerator the DB400 Clock Buffer the ispPOWR1220A power monitor sequencer various Temperature monitoring devices and an I2C bus expander PEX8624 PECI MON DUAL T S 82599 XMC 1 XMC 2 ispPOWR1220A I2C BUS MULTIPLEXER VPX RTM CK505 CLK x4 MAX7500 T S DB400 82571 SFP I2C BUS EXP XDP DEBUG ICH9R FM3224 MCH DDR2 SPD DDR2 SPD ICH_SMB SMB_B SMB_A DDR2_SMB FM_SMB Figure 9 SMBus Architecture The I2C bus expan...

Page 21: ... s control backend 3 3 and 5V power 12V is generated by an LTC3693 1A regulator and is only used by the dual PMC sites Power monitoring and sequencing is performed by a programmable Lattice ispPOWR1220A VPX P0 LTM4616 LTM4616 LTM4616 LTM4616 LTM4616 LTM4616 LTM4616 LTM4616 ispPOWR 1220A POWER MONITOR AND SEQUENCER ISL6314 FET SWITCH FET SWITCH LTC3693 V3_3_EP V1_8 V1_5 V1_2 P_VTT V1_05 V0_9 VCORE ...

Page 22: ...s dual 1Gb Ethernet ports a RS232 485 Console port and a VGA port Four 2mm headers are provided to support CPU 111 10 PMC Module I O J1 and J3 terminate the signals derived from PMC J14 and J2 and J4 terminate signals from J24 Please refer to Appendix D for RTM pin assignments SFP CX4 COPPER FIBER INTERFACE Netlogic AEL2005 XAUI to SFI PHY POL USB1 USB0 ETH1 ETH0 SFP eSATA1 eSATA2 eSATA3 eSATA4 RS...

Page 23: ...X system for single slot operation This chapter should be read in its entirety before proceeding with the installation 4 1 Selectable Options This section explains how to set up user configurable jumpers The CPU 111 10 is shipped in an antistatic bag Be sure to observe proper handling procedures during the configuration and installation process to avoid damage due to electrostatic discharge ESD Th...

Page 24: ...Chapter 4 Installation Dynatem CPU 111 10 Intel Xeon Quad Core 6U VPX SBC User s Manual 19 Figure 12 CPU 111 10 Connectors and Headers ...

Page 25: ...o PMC XMC sites an SFP connector and an optional USB port Front panel indicators consist of a green power on LED a red CPU Error LED a yellow System Controller LED and a yellow solid state drive activity LED A small hole is provided for access to recessed reset switch CPD 111 10 SFP PMC XMC SITE 2 PMC XMC SITE 1 PWR ON CPU ERR SSD ACT SYS CON RESET USB Figure 13 Front Panel Connectors and Indicato...

Page 26: ...Differential Differential Differential Differential Differential GND GND GND SYS_CON GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND XAIU2_RX0 XAIU2_RX2 XAIU2_RX0 XAIU2_RX1 XAIU2_RX2 XAIU2_RX3 XAIU2_RX3 XAIU2_RX1 XAIU2_TX0 XAIU2_TX2 XAIU2_TX3 XAIU2_TX0 XAIU2_TX1 XAIU2_TX2 XAIU2_TX3 XAIU2_TX1 XAUI0_R...

Page 27: ...5_RX1 XAIU5_RX0 XAIU5_TX3 XAIU5_RX3 XAIU5_TX3 XAIU5_RX3 User Defined Data Plane 5 Fat Pipe 10GBASE BX4 VITA 46 9 r0 23 XMC Site 1 X12d Pattern Map Table 4 VPX P3 Connector Pin outs Wafer Type Row G Row F Row E Row D Row C Row B Row A J14 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 J14 3 J14 7 J14 11 J14 15 J14 5 J14 9 J14 13 J14 23 J14 27 J14 31 J14 21 J14 25 J14 29 J14 33 J14 35 J14 39 J14 43 J14 47...

Page 28: ...2_CTS or RS485_RX MDXB_0 MDXB_0 MDXB_1 MDXB_1 MDXB_2 MDXB_2 MDXB_3 MDXB_3 VGA_SDA Control Plane 1 Thin Pipe 1000 BASE T Control Plane 2 Thin Pipe 1000 BASE T OpenVPX MOD6 PAY 4F2T 12 2 2 4 User Defined Data Plane 6 Fat Pipe 10GBASE BX4 User Defined User Defined User Defined 4 Serial ATA 2 USB Serial Comm 2 Ultra Thin Pipes Table 6 VPX P5 Connector Pin outs XAIU7_TX2 XAIU7_RX2 XAIU7_TX2 XAIU7_RX2 W...

Page 29: ...CK GND AD 15 AD 12 AD 9 GND AD 6 AD 11 V5_0 C BE 0 AD 5 AD 4 VIO AD 2 AD 0 GND AD 3 AD 1 V5_0 GND REQ64 V12_P Pin 1 2 3 4 5 6 7 8 Pin 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 J12 J22 GND GND RESET V3_3 V3_3 PME AD 30 GND GND AD 29 AD 26 AD 24 IDSEL V3_3 AD 18 V3_3 AD 23 AD ...

Page 30: ...RX7p GND WAKE 17 18 19 PE1_RX6p GND REFCLKp PE1_RX6n GND REFCLKn PE1_RX7n GND V3_3 V3_3 V3_3 V3_3 GA1 b0 V3_3 GA2 b0 NVMRO Row F Row E Row D Row C Row B Row A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 XA6_TX1p GND XA6_TX3p GND P26_DP05p GND P26_DP07p GND P26_DP09p GND XA6_RX1p GND XA6_RX3p GND P26_DP15p GND J26 Secondary Site 2 XMC Connector 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 XA6_TX0p GND XA6_TX2...

Page 31: ...endix A Connector Pinouts Dynatem CPU 111 10 Intel Xeon Quad Core 6U VPX SBC User s Manual 26 A 5 Front Panel USB Pin out Table 11 USB Connector Pin out Signal Pin 5V 1 USB 2 USB 3 GND 4 USB Connectors 1 4 ...

Page 32: ...lete Del key on your keyboard after powering up your system during POST B 1 Redirecting to a Serial Port Setup may be run from the main keyboard and video display or from a terminal emulator program running on a host computer connected to the system through a serial cable To use a serial port connect a dumb terminal or a PC running a terminal emulation utility like Hyperterminal to COM1 via a null...

Page 33: ...cations Chipset Configure any chipset specific parameters such as memory CPU and bus timing and availability of chipset specific features such as TFT support Highly platform specific and entirely up to the OEM s implementation B 3 Navigating Setup Menus and Fields Navigation moving your cursor around selecting items and changing them is easy in theSetup system The following chart is a helpful user...

Page 34: ...ay be desirable to reenter the Setup system as necessary to adjust settings as necessary Once the system boots the Setup system cannot be entered this is because the memory used by the BIOS configuration manager is deallocated by the system BIOS so that it can be used by the OS when it boots To reenter the Setup system after boot simply reset the system or power off and power back on B 4 Main Setu...

Page 35: ...ubtracting RAM used for System Management Mode Shadowing Video buffers and other uses This provides realistic values about how much memory is actually available to operating systems and applications The Real Time Clock fields are editable with keystrokes To navigate through the MM DD YYYY and HH MM SS fields use the TAB and BACKTAB keys The hours are normally specified in military time thus 13 mea...

Page 36: ...e list become candidates for booting the OS The BBS list also contains other boot actions such as boot from network cards and PCI slots as well as special BIOS boot actions like Boot EFI Boot Windows CE or even Boot Debugger When deciding what boot action to do first and then next in succession POST first scans all the drives in the list to verify they are present and operating properly as describ...

Page 37: ...phical Firmbase applications as well as booting DOS in a graphical window For applications requiring instant on functionality even when the OS is not available or is still loading The photograph above shows a common setup of the BBS list for desktop applications In this example the first boot device is theWestern Digital IDE hard drive WDC WD800JB 00JJC0 connected to the target as a Primary Master...

Page 38: ...his setting to 80 pin or AUTO if an 80 pin cable is installed B 7 POST Setup Menu The POST menu is used to configure POST This menu is shown in the following figure scrolled down more so the full set of options can be seen Be sure to review the Features menu where additional items can be configured such as the Splash Screen and BIOS initiatives The figure below shows the same menu scrolled down so...

Page 39: ...Appendix B BIOS Setup Dynatem CPU 111 10 Intel Xeon Quad Core 6U VPX SBC User s Manual 34 ...

Page 40: ... POST is configured to ask interactive questions of the user about whether to load specific features i e whether or not to load SMM POST Display PCI Devices Enable display of PCI devices POST Display PnP Devices Enable display of ISA PnP devices The following table describes the settings associated with the POST setup menu s Debugging section POST Debugger Breakpoints Enable processing of INT 3 br...

Page 41: ... greyed out Enable to support legacy OSes like DOS Windows95 Windows98 and WindowsNT Disable for operating systems like WindowsXP or Windows Vista or for Linux operating systems with ACPI support Plug n Play OS Enable delay of configuration of PnP hardware and option ROMs When enabled BIOS will NOT configure the devices and instead defer assignment of resources such as DMA I O memory and IRQs to t...

Page 42: ...nd two 2 wire COM ports COM3 COM4 Basically this window is used to configure COM3 COM4 though they are referred to as Serial Ports 1 2 in the SIO Setup Menu POST reads these settings in the menu shown above and programs the Super I O part accordingly enabling and disabling devices as requested The disabled devices are not further programmed since they are actually disabled in hardware In the figur...

Page 43: ...ower management ACPI replaces PnP and APM Used with ACPI aware OSes such as Linux kernels version 2 6 and above Windows XP and Windows Vista Commonly also uses the SMM feature see Firmbase to operate properly POST Memory Manager PMM Enable memory allocation services for option ROMs especially network cards running PXE Some option ROMs may use this interface incorrectly causing system crashes Other...

Page 44: ...ce B 11 Firmbase Setup Menu The Firmbase menu configures the Firmbase Technology component of the system BIOS including all of the features enabled by it i e legacy USB keyboard and mouse boot from USB devices and support of Firmbase applications such as Boot Security Platform Update Facility and High Availability Monitor This menu has several parts with the most basic user oriented feature option...

Page 45: ...se Debug Log Specifies the device used by Firmbase Technology components kernel drivers and programs to display debugging instrumentation produced with the dprintf and DPRINTF system functions None Instrumentation disabled COM1 Write text to 1st serial port COM2 Write text to 2nd serial port COM3 Write text to 3rd serial port COM4 Write text to 4th serial port Virtual Write text to virtual console...

Page 46: ... operate correctly B 12 Miscellaneous Setup Menu The Misc menu provides for configuration of BIOS settings that don t easily fit in any other category They include Cache Control Keyboard Control Debugger Settings and System Monitor Utility Configuration parameters The following table presents the settings in the Misc Setup menu System Cache Enables POST s support for cache in the system Modern pro...

Page 47: ...sk Write Stimulation Enables System Monitor s write of a preconfigured number of sectors to a location on the first hard disk in the system in order to stimulate the SMM environment This is useful when measuring code path lengths in USB boot when the first hard drive is configured in the BBS list as a USB hard drive Please note that when this parameter is selected the system automatically enables ...

Page 48: ...hrottling can be implemented for wider temperature ranges Storage 50 C to 85 C Humidity Operating 20 to 95 non condensing 4 relative humidity per MIL STD 810F Storage 0 to 100 non condensing Altitude Unlimited Vibration Sine 10g peak 15 2 kHz All levels based on a sweep duration of 10 minutes per axis each of three mutually perpendicular axes Qualification testing is displacement limited below 44 ...

Page 49: ...XAUI7 TX0 1 GND 2 XAUI7 TX2 3 GND XAUI7 TX3 XAUI7 TX3 GND 4 GND 5 GND GND 6 Differential GND 7 Differential GND GND 8 GND GND XAUI7 TX1 XAUI7 TX0 XAUI7 TX1 GND XAUI7 TX2 9 GND 10 11 GND GND 12 GND 13 GND GND 14 Differential GND 15 Differential GND GND 16 GND GND GND Differential Differential Differential Differential Differential Differential Differential Differential Differential Differential Dif...

Page 50: ...J14 10 J14 14 J14 18 J14 22 J14 26 J14 30 J14 34 J14 38 J14 42 J14 46 J14 50 J14 54 J14 58 J14 62 J14 4 J14 8 J14 12 J14 16 J14 20 J14 24 J14 28 J14 32 J14 36 J14 40 J14 44 J14 48 J14 52 J14 56 J14 60 J14 64 Table 17 RTM VPX RP6 Pin outs Wafer Type Row G Row F Row E Row D Row C Row B Row A J24 1 1 2 3 GND 4 GND 5 GND 6 GND 7 GND 8 GND GND GND 9 10 11 GND 12 GND 13 GND 14 GND 15 GND 16 GND GND GND ...

Page 51: ...J24 46 J24 50 J24 54 J24 58 J24 62 J24 4 J24 8 J24 12 J24 16 J24 20 J24 24 J24 28 J24 32 J24 36 J24 40 J24 44 J24 48 J24 52 J24 56 J24 60 J24 64 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND J24 1 J24 3 J24 7 J24 11 J24 15 J24 5 J24 9 J24 13 J24 17 J24 19 J24 23 J24 27 J24 31 J24 21 J24 25 J24 29 J24 33 J24 35 J24 39...

Page 52: ...Appendix D XPDDRIO Rear Plug in I O Expansion Module for the CPU 111 10 Dynatem CPU 111 10 Intel Xeon Quad Core 6U VPX SBC User s Manual 47 ...

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