Installation, Operation and Service Manual
LKP Series 4 Channel OEM
© 2019 DynAmp, LLC
Page 20
041593O
5.4 METERING UNIT
Although the Metering Unit contains only an isolation transformer and two circuit boards, it is
comprised of several sub-circuits. Each of these circuits is described in the remaining
paragraphs.
5.5 POWER SUPPLIES
There are two power supplies on the LKP Series 4 Channel OEM Metering Unit; the +7 Vdc
(12 Vdc for LKP-15 & 30) supply and the ±15 Vdc supply. The ±15 Vdc power supply powers
only the on-board circuitry. The +7 (or -12Vdc) supply powers the Hall devices in the
Measuring Head. The SCR bridge is powered directly by the ac line voltage.
5.6 SYNC, PLL, AND RAMPS
The Metering Unit employs phase locked loop circuitry for synchronization of the firing pulses of
the SCRs. This particularly is an advantage when there is a high noise level present on the line
voltage. The PLL circuitry consists of U101, U102, and associated circuitry (see Metering Unit
schematic drawing). The line voltage is sensed at TP-4. It is then filtered and sent to U112 to
be converted into a square wave, and then to the PLL circuitry. The output of the PLL is a
squarewave and is present at TP-2. This signal is sent to U104, U105, and RP101, which
constitutes the ramp generator. The ramp generator output consists of two downward sloping
ramps, each 180 degrees in phase from one another. Both ramps are sent to the quad
comparators (U110 and U111), which are used to generate the firing pulses for the SCRs.
5.7 ERROR AMPLIFIERS
The error amplifier circuitry consists of U106 through U109 and associated circuitry. The error
amplifiers serve two purposes, to amplify the Hall error signal and to filter it before sending it to
the comparators.
5.8 COMPARATORS AND PULSE GENERATOR
The comparators consist of U110 and U111. They compare the amplified/filtered output of the
error amplifiers to the two ramps generated by PLL and ramp generators. Two squarewaves
are generated at the output of these comparators, one for the positive half cycle and one for the
negative half, (pins 1 and 2 of U110 for channel #1). One square wave will be used to trigger an
SCR on the positive half of the waveform, and the other will be used for the other half cycle.
Since these squarewaves are too long in duration, they cannot be used directly to drive the
pulse transformer drivers. The comparator output is "ANDed" (the mathematical product of a
logic AND gate) with several pulses generated by the PLL. The output, (pins 3 and 4 on U113
for channel #1) will be a pulse train, which will be used to drive the pulse transformer drivers.
Pulse train triggering is an advantage when noise on the line turns off an SCR. The SCR is re-
triggered allowing a minimum off time. Since these pulses are fixed and do not move, if they
alone are used to drive the SCRs, the output would be very jumpy. The pulse train is smoothed
by also ANDing the comparator with an integrated output of itself to give the output pulse train
infinite resolution.
