RC907/908-EV35 User Guide
not only prevent long time delay, but also avoid packet loss caused by sudden data
flooding. It is suggested that the buffer size be configured as the following table.
DIP-switch
WAN Interface Rate (bit/s)
3rd Bit
4th Bit
5th Bit
≥
2M OFF
OFF
OFF
> 1M
OFF
ON
ON
> 512K
ON
OFF
ON
> 256K
ON
ON
OFF
> 64K
ON
ON
ON
≤
64K ON
ON
ON
m
The 6th bit: TX CLK phase selection switch.
It provides various options for different phase relationships of transmitting data and
TX clocking at V.35 interface between different brands DCE equipment.
OFF: positive phase (default).
ON: negative phase.
m
The 7th bit: RX CLK phase selection switch.
It provides various options for different phase relationships of receiving data and
RX clocking at V.35 interface between different brands DCE equipment.
OFF: positive phase (default).
ON: negative phase.
m
The 8th bit: Reserved bit.
The factory default setup of the dip-switch:
DIP-switch 1
2
3
4
5
6
7
8
ON
OFF
■
■
■
■
■
■
■
■
Details
Half
duplex
Fault
Pass
Through
disabled
Maximum buffer size
Positive
phase
Positive
phase
No
Meaning
Note:
1. Please use the 1st bit to configure the half/full duplex mode of converters
following the instructions in 2.3 Full Duplex Mode Configuration, Chapter 2.