Embedded Solutions
Page 11 of 37
The PLL is configured to supply a 48 MHz signal on its clock A output. This is used to
sample the transmit reference clock to detect transitions. These transitions are used to
determine when to drive the next data bit onto the transmit data I/O line. The
transmitter clock reference can be supplied by an external source or an internal clock
reference provided by PLL clock B. For test purposes, a substitute external clock is
created by routing the output from PLL clock B onto I/O 32 and 33 configured as
outputs. These clocks may be connected externally to any or all selected channels for
loopback testing. A control bit in each channels control register is used to select
between these two options. When the internal clock mode is selected the transmit
clock line is configured as an output, but when the external clock mode is selected the
transmit clock line is configured as an input. The transmit data line is always an output
and the receive clock and data lines are always inputs.
