Dynamic Engineering PCI3IP-Minimap User Manual Download

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Page 3 Electronics Design • Manufacturing Services

Table of Contents

PRODUCT DESCRIPTION

THEORY OF OPERATION

ADDRESS MAP

PROGRAMMING

Register Definitions

pci3ip_intreg0

pci3ip_intreg1

pci3ip_intreg2

APPLICATIONS GUIDE

Interfacing

Construction and Reliability

Thermal Considerations

WARRANTY AND REPAIR

Service Policy

Out of Warranty Repairs

For Service Contact:

SPECIFICATIONS

ORDER INFORMATION

Summary of Contents for PCI3IP-Minimap

Page 1: ...831 336 8891 Fax 831 336 3840 http www dyneng com sales dyneng com Est 1988 User Manual PCI3IP Minimap PCI 3 Slot IP Compatible Carrier 2KB Address Space Manual Revision A Corresponding Hardware Revi...

Page 2: ...ribed in this document at any time and without notice Furthermore Dynamic Engineering assumes no liability arising out of the application or use of the device described herein The electronic equipment...

Page 3: ...P 9 PROGRAMMING 10 Register Definitions 11 pci3ip_intreg0 11 pci3ip_intreg1 13 pci3ip_intreg2 14 APPLICATIONS GUIDE 15 Interfacing 15 Construction and Reliability 15 Thermal Considerations 17 WARRANTY...

Page 4: ...Manufacturing Services List of Figures FIGURE 1 PCI3IPMM ADDRESS MAP 9 FIGURE 2 PCI3IPMM CONTROL PORT 11 FIGURE 3 PCI3IPMM INTERRUPT STATUS PORT 13 FIGURE 4 PCI3IPMM USER SWITCH PORT 14 FIGURE 5 PCI3I...

Page 5: ...t data will be returned For example a long word read to the ID space would yield 0xff50ff49 for many boards as the 0 location has 49 and the next address has 50 The long word mode happens automaticall...

Page 6: ...reset is controlled to be synchronous to the 8 MHz clock Alternatively in development the IP Debug Bus card also has a reset switch which allows for individual slot resets The IO are brought to 50 pin...

Page 7: ...ng word access Incrementing or static access to each IP slot from long word access Bus error abort response 1 1 50 pin headers with 012 traces between IO and header IP Reset Switch 8 position DIP Swit...

Page 8: ...Design Manufacturing Services The basic PCI identifying information will not change with the updates The revision field will allow configuration control Current revision is 0x01 Firmware Revision Tabl...

Page 9: ...b_en 0x000005ff end address slot B MEM space define pci3ip_idc_st 0x00000600 start address slot C ID space define pci3ip_ioc_st 0x00000680 start address slot C IO space define pci3ip_intc_st 0x0000070...

Page 10: ...We use a program called WinRT to do the low level accesses to the hardware We use MS Visual C in conjunction with WinRT to write our test software Please feel free to copy the following set up code o...

Page 11: ...Word Access B 14 Increment Disable B 13 High Word Access A 12 Increment Disable A 11 INT FORCE 1 FORCE 0 NORMAL 10 INT EN C1 1 ENABLED 0 DISABLED 9 INT EN C0 8 INT EN B1 7 INT EN B0 6 INT EN A1 5 INT...

Page 12: ...types of access are affected i e MEM IO INT and ID Only 32 bit accesses are affected High Word Access A B C controls which 16 bit word is accessed when the Increment Disable is asserted When 0 the lo...

Page 13: ...SET 0 NOT SET 7 INTRN 1 SET 0 NOT SET 6 INT FORCE 5 MASKED C1 4 MASKED C0 3 MASKED B1 2 MASKED B0 1 MASKED A1 0 MASKED A0 1 SET 0 NOT SET FIGURE 3 PCI3IPMM INTERRUPT STATUS PORT The interrupt request...

Page 14: ...register The Bus Error status bit is OR d into the interrupt request logic and if enabled will cause a level sensitive interrupt to the host The interrupt will remain asserted until the status is clea...

Page 15: ...ise immunity Power supplies and power consuming loads should all have their own ground wires back to a common point Power all system power supplies from one switch Connecting external voltage to the P...

Page 16: ...y or is in an environment subject to high vibration the user may solder the corner pins of each socketed IC into the socket using a grounded soldering iron The IP Module connectors are keyed and shrou...

Page 17: ...ranty Dynamic Engineering s sole responsibility shall be to repair or at Dynamic Engineering s sole option to replace the defective product The product must be returned by the original customer insure...

Page 18: ...es due to improper packaging of returned items For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller Products returned to Dynamic Engineerin...

Page 19: ...ntrol registers Access Time Typical access time with 32 MHz IP and double access mode is 500 ns Interrupt 2 Interrupts per IP slot with separate enables DMA No DMA Support implemented at this time Onb...

Page 20: ...com ipdbgbus html IP test points reset switch fused power quick switch isolated interface lines to allow hot swapping of IP cards IP DEBUG IO http www dyneng com ipdbgio html Isolate the IO connector...

Page 21: ...A B C and three header connectors associated with those slots The wiring is 1 1 from the IP IO connector to the PCI3IP header connector The connectors are numbered to match standard ribbon cable as s...

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