Page 12 Electronics Design • Manufacturing
S
i
Spare means unused and unplanned
RES means unused and planned for future enhancements
INT FORCE will when set cause INTA on the PCI bus to be asserted. This bit
can be useful for software debugging. Set this to simulate an IP interrupt
when the hardware is not available.
INT EN A0..C1 individual masks for the 2 interrupts from each of the three
slots. 0 corresponds to INT0 and 1 corresponds to INT1.
CLK SEL Default is set to cause the statemachine for the IP interface to
operate at 32 MHz. when not accessing IP hardware. 0 sets the default
speed to 8 MHz.
CLK SEL A,B,C are used to select the slot clock speed.
1 = 32 MHz. 0 = 8 MHz. PLL used to generate and low skew drivers to
allow switching the clock speed on-the-fly.
Increment Disable A,B,C, when ‘1’, turns off the address increment, for the
respective slot, that normally occurs between 16-bit IP cycles when a 32-
bit PCI access is performed. This is useful if, for instance, a FIFO is mapped
to a single IP address since it allows double IP accesses to the same
address with a single PCI transfer. All types of access are affected (i.e.
MEM, IO, INT, and ID). Only 32 bit accesses are affected.
High Word Access A,B,C controls which 16-bit word is accessed when the
Increment Disable is asserted. When ‘0’ the lower word is accessed twice,
when ‘1’ the upper word is accessed twice. This bit only has an effect when
the Increment Disable bit is ‘1’. For correct functioning, make sure the PCI
access is on a long-word boundary.
Bus Error Int En when ‘1’ allows the bus error detection circuit to cause an
interrupt to the host when a Bus Error is detected. The status is available
on the Interrupt status register. When ‘0’ the status is still valid but no
interrupt is generated when a bus error is detected. The bus error is
detected when an access to one of the 3 IP slots is not responded to by IP
hardware within the time-out period of approximately 7.6 us. The bus error
circuit is always enabled and automatically responds as if the IP had
responded. The data read will typically be $FF if the IP is not driving the bus
for a bus error read. For a bus error write the write should be assumed to
not have taken place. The host will not know that the bus error has taken
place unless the host checks the status. The interrupt can provide a
prompt to check the status during operation. During initialization if the
