T5L_ASIC Development Guide
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3.9 Interrupt System
3.9.1Interrupt Control SFR
T5L OS CPU has 12 interrupts. The related control SFRs list is as follows:
SFR
name
Address
Instructions
IEN0
0xA8
The interrupt enable controller 0 can be addressed by bit.
.7 Interrupt master control bit. 0=all interrupts closed; 1=whether an interrupt is opened is controlled by the
control bit of each interrupt;
.6 Must write 0;
.5 ET2 T2 timer interrupt enable control bit;
.4 ES0 UART2 interrupt enable control bit;
.3 ET1 T1 timer interrupt enable control bit;
.2 EX1 external interrupt 1 (P3.1 pin) interrupt enabling control bit;
.1 ET0 T0 timer interrupt enable control bit;
.0 EX0 external interrupt 1 (P3.0 pin) interrupt enabling control bit.
IEN1
0xB8
The interrupt enable controller 1 can be addressed by bit.
.7-.6 Write 0;
.5 ES3R UART5 receiving interrupt enabled control bit;
.4 ES3T UART5 receiving interrupt enabled control bit;
.3 ES2R UART4 receiving interrupt enabled control bit;
.2 ES2R UART4 receiving interrupt enabled control bit;
.1 ECAN CAN communication interrupt enabling control bit;
.0 Write 0.
IEN2
0x9A
Interrupt enabling controller 2
.7-.1 Must write 0
.0 ESI USRT3 interrupt enabling control bit
IEN3
0xD1
Interrupt enabling controller 3, must write 0x00
IP0
0xA9
Interrupt priority controller 0
IP1
0xB9
Interrupt priority controller 1
