
5.2.1.2 Charge Transfer
During the Vertical blanking interval, the charge that was integrated in each active charge site
during the previous exposure (normally 1/12 sec, or one frame) is shifted to an adjacent opaque
storage charge site. In the figure below, active charge sites are designated by the letter “I” for
integration and the opaque storage charge sites are designated by the letter “S” for storage.
S
I
S
I
S
I
S
I
S
S
I
S
I
S
I
S
I
S
S
I
S
I
S
I
S
I
S
S
I
S
I
S
I
S
I
S
S
I
S
I
S
I
S
I
S
S
I
S
I
S
I
S
I
S
S
I
Charge transfer
(once per frame)
S
I
S
I
S
I
S
I
S
S
I
S
I
S
I
S
I
S
S
I
S
I
S
I
S
I
S
S
I
S
I
S
I
S
I
S
S
I
S
I
S
I
S
I
S
S
I
S
I
S
I
S
I
S
H-line transfer
Charge detection node
Horizontal shift register
1300 columns
1030
r
ow
s
Figure 5.2-2: Block diagram of CCD
5.2.1.3 Readout
In the following adjacent frame, the charges are transferred vertically, one line at a time, from the
storage charge sites of the CCD to an on-chip horizontal shift register and then sequentially to the
detection node where they are made available as signal voltages.
Note:
While one frame is being
read out from the opaque pixels, the next frame is being integrated in the active charge sites of the
CCD.
5.2.2 Video
Processing
The low-level video signal voltage from the CCD is clamped (for black reference) and fed through
a high-speed CDS correlated double sampling CDS amplifier. The CDS process is required to
remove a significant source of noise from the video signal. The video signal is then amplified in the
next stage, which has voltage-controlled-gain and voltage-controlled-offset. The control voltages
for gain and offset are 0 to 3V in range and are derived via on-board digital-to-analog converters
(DACs) which are controlled via the host PC interface.
5.2.3 Video
Digitization
The video signal output from the video processor is fed to a 12-bit Analog-to-Digital converter.
The 12 bit digital date is available at a connector on the board.
14