
46
AGP Driving
Value
00-FF
This value sets the timing of the signal that the video card
driver uses to communicate over the AGP bus. The range is
from 00-FF Hex (00-255 DEC).
AGP Bus Timing Setting
Values
Meaning
Enabled
AGP Writes are executed with 1 wait state, enable only if your
AGP card support this.
AGP Master
1 WS Write
Disabled
AGP Write take longer than 1 wait state, default setting.
Enabled
AGP Reads are executed with 1 wait state, enable only if your
AGP card supports this.
AGP Master
1 WS Read
Disabled
AGP Reads take longer than 1 wait state, default setting.
Phienix – AwardBIOS CMOS Setup Utility
CPU & PCI Bus Control
PCI1 Master 0 WS Write
Enabled
Item Help
PCI2 Master 0 WS Write
Enabled
Menu Level
"
PCI1 Post Write
Enabled
PCI2 Post Write
Enabled
PCI Delay Transaction
Disabled
↑
↓
→
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F5 : Previous Values F6:Fail-Safe Defaults F7: Optimized Defaults
PCI Bus Timing Setting
Values
Meaning
Enabled
PCI1 Master
0 WS write
Disabled
Enabled
PCI2 Master
0 WS write
Disabled
Enabled
PCI1 Post
Write
Disabled
Enabled
PCI2 Post
Write
Disabled
PCI delay
Transaction
Enabled
The chipset has a write buffer that supports delayed
transactions. Enable this item for PCI 2.1 compliance.