5.3
Display Panels
dimtel
dimtel
DCM PHASE
ADC data acquisition phasing. This parameter is config-
ured at the factory and does not need to be adjusted in operation.
FID CLOCK OFFSET
Offset between the ADC clock and the fiducial
clock. This parameter is configured at the factory and does not need
to be adjusted in operation.
FID SIGNAL OFFSET
This offset sets the relative timing of the input
fiducial signal and the fiducial receiving clock. This setting must be
optimized after installation. To do so, connect the RF clock and the
fiducial in the final (operational) configuration. Then, adjust the fidu-
cial delay to find the error range. Let us consider, for example, RF
frequency of 368 MHz. The RF period is 2700 ps. Within one period
there should be a range of delays in which the fiducial is jittering across
the RF clock and the fiducial error indicator is red. By moving the de-
lay in steps of 100 ps find the beginning (
N
1
) and the end (
N
2
) of this
range. The optimal setting is at (
N
1
+
N
2
)
/
2
±
1350 ps.
DAC OFFSET
Offset between FPGA data and DAC clock. This param-
eter is configured at the factory and does not need to be adjusted in
operation.
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