29 September 1997 – Subject To Change
Electrical Data
9–17
AC Characteristics
Signals in Table 9–11 are used to control Bcache data transfers. These signals are
driven off the CPU clock. The timing of these signals does not change when switch-
ing over to the sys_clk_out timing domain.
9.4.4 Timing of Test Features
Timing of 21164PC testability features depends on the system clock rate and the test
port’s operating mode. This section provides timing information that may be needed
for most common operations.
9.4.4.1 Icache BiSt Operation Timing
The Icache BiSt is invoked by deasserting the external reset signal sys_reset_l.
Figure 9–6 shows the timing between various events relevant to BiSt operations.
1
The value 0.2 ns accounts for onchip driver and clock skew.
2
For big drive enabled or big drive disabled, respectively. See Table 9–7.
Table 9–11 Bcache Control Signal Timing
Signal
Specification
Value
Name
Input mode:
tag_data_h, tag_data_par_h,
tag_valid_h
Input setup
1.1 ns
Tdsu
tag_data_h, tag_data_par_h,
tag_valid_h
Input hold
0 ns
Tdh
Output mode:
data_ram_oe_l, data_ram_we_l<3:0>,
tag_ram_oe_l, tag_ram_we_l
Output delay
Tbedd + 0.2 ns or
Tbddd + 0.2 ns
1,2
Taod
tag_data_h, tag_data_par_h,
tag_valid_h
Output delay
Tdd + 0.2 ns
Taod
data_ram_oe_l, data_ram_we_l<3:0>,
tag_ram_oe_l, tag_ram_we_l
Output hold
Tmdd
Taoh
tag_data_h, tag_data_par_h,
tag_valid_h
Output hold
Tmdd
Taoh
