29 September 1997 – Subject To Change
Initialization and Configuration
7–5
Input Signals sys_reset_l and dc_ok_h and Booting
While signal dc_ok_h is deasserted, the 21164PC provides its own internal clock
source from an onchip ring oscillator. When dc_ok_h is asserted, the 21164PC clock
source is the differential clock input pins osc_clk_in_h,l.
When the 21164PC is free-running from the internal ring oscillator, the internal
clock frequency is in the range of 10 MHz to 100 MHz (varies from chip to chip).
The sysclk divisor and sys_clk_out2_h delay are determined by input pins while
signal sys_reset_l remains asserted. Refer to Section 4.2.2 and Section 4.2.3 for ratio
and delay values.
7.1.1 Pin State with dc_ok_h Not Asserted
While dc_ok_h is deasserted, and sys_reset_l is asserted, every output and bidirec-
tional 21164PC pin is tristated and pulled weakly to ground by a small pull-down
transistor.
srom_data_h
NA (input).
srom_oe_l
Deasserted.
srom_present_l
NA (input).
tck_h
NA (input).
tdi_h
NA (input).
tdo_h
NA (input).
temp_sense
NA (input).
test_status_h<1>
Deasserted.
tms_h
NA (input).
trst_l
Must be asserted (input).
Table 7–1 21164PC Signal Pin Reset State
(Sheet 3 of 3)
Signal
Reset State
