Digilent Nexys2 Reference Manual Download Page 8

Nexys2 Reference Manual 

 

Digilent 

www.digilentinc.com 

 

Copyright Digilent, Inc. 

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                                  Doc: 502-134 

 

device can illuminate state LEDs on the keyboard). 
Bus timings are shown in the figure. The clock and 
data signals are only driven when data transfers 
occur, and otherwise they are held in the “idle” 
state at logic ‘1’. The timings define signal 
requirements for mouse-to-host communications 
and bi-directional keyboard communications. A 
PS/2 interface circuit can be implemented in the 
FPGA to create a keyboard or mouse interface. 
 
 
Keyboard 
 
The keyboard uses open-collector drivers so the keyboard or an attached host device can drive the 
two-wire bus (if the host device will not send data to the keyboard, then the host can use input-only 
ports). 
 
PS2-style keyboards use scan codes to communicate key press data. Each key is assigned a code 
that is sent whenever the key is pressed; if the key is held down, the scan code will be sent repeatedly 
about once every 100ms. When a key is released, a “F0” key-up code is sent, followed by the scan 
code of the released key. If a key can be “shifted” to produce a new character (like a capital letter), 
then a shift character is sent in addition to the scan code, and the host must determine which ASCII 
character to use. Some keys, called extended keys, send an “E0” ahead of the scan code (and they 
may send more than one scan code). When an extended key is released, an “E0 F0” key-up code is 
sent, followed by the scan code. Scan codes for most keys are shown in the figure. A host device can 
also send data to the keyboard. Below is a short list of some common commands a host might send. 
 
ED 

Set Num Lock, Caps Lock, and Scroll Lock LEDs. Keyboard returns “FA” after receiving “ED”, 
then host sends a byte to set LED status: Bit 0 sets Scroll Lock; bit 1 sets Num Lock; and Bit 2 
sets Caps lock. Bits 3 to 7 are ignored.  

EE 

Echo (test). Keyboard returns “EE” after receiving “EE”. 

F3 

Set scan code repeat rate. Keyboard returns “F3” on receiving “FA”, then host sends second 
byte to set the repeat rate. 

FE 

Resend. “FE” directs keyboard to re-send most recent scan code. 

FF 

Reset. Resets the keyboard. 

 
The keyboard can send data to the host only when both the data and clock lines are high (or idle). 
Since the host is the “bus master”, the keyboard must check to see whether the host is sending data 
before driving the bus. To facilitate this, the clock line is used as a “clear to send” signal. If the host 
pulls the clock line low, the keyboard must not send any data until the clock is released. The keyboard 
sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by 8-bits of scan code (LSB 
first), followed by an odd parity bit and terminated with a ‘1’ stop bit. The keyboard generates 11 clock 
transitions (at around 20 - 30KHz) when the data is sent, and data is valid on the falling edge of the 
clock. 
 
Scan codes for most PS/2 keys are shown in the figure below. 
 
 
 
 

 

Figure 13: PS/2 signal timings 

Summary of Contents for Nexys2

Page 1: ...nd a host of sensor and actuator interfaces All user accessible signals on the Nexys2 board are ESD and short circuit protected ensuring a long operating life in any environment The Nexys2 board is fu...

Page 2: ...ply and 100mA from the 3 3V supply Required current will increase if larger circuits are configured in the FPGA and if peripheral boards are attached The table above summarizes the power supply parame...

Page 3: ...e USB port A jumper on the Nexys2 board determines which source PC or ROM the FPGA will use to load its configuration The FPGA will automatically load a configuration from the Platform Flash ROM at po...

Page 4: ...udes a 50MHz oscillator and a socket for a second oscillator Clock signals from the oscillators connect to global clock input pins on the FPGA so they can drive the clock synthesizer blocks available...

Page 5: ...rent A ninth LED is provided as a power on LED and a tenth LED indicates FPGA programming status Note that LEDs 4 7 have different pin assignments due to pinout differences between the 500 and the 120...

Page 6: ...ter of the time but because the eye cannot perceive the darkening of a digit before it is illuminated again the digit appears continuously illuminated If the update or refresh rate is slowed to around...

Page 7: ...s 500mA and then activates a transistor switch to connect the USB cable voltage to the main input power bus The Nexys2 board typically draws around 300mA from the USB cable and care should be taken es...

Page 8: ...scan code When an extended key is released an E0 F0 key up code is sent followed by the scan code Scan codes for most keys are shown in the figure A host device can also send data to the keyboard Belo...

Page 9: ...period is 20 to 30KHz The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field and moving to the left generates a negative numbe...

Page 10: ...precise information or for information on other VGA frequencies refer to documentation available at the VESA website CRT based VGA displays use amplitude modulated moving electron beams or cathode ra...

Page 11: ...to right and top to bottom and not during the time the beam is reset back to the left or top edge of the display Much of the potential display time is therefore lost in blanking periods when the beam...

Page 12: ...erived Timings for sync pulse width and front and back porch intervals porch intervals are the pre and post sync pulse times during which information cannot be displayed are based on observations take...

Page 13: ...tatic DRAM device organized as 8Mbytes x 16bits It can operate as a typical asynchronous SRAM with read and write cycle times of 70ns or as a synchronous memory with an 80MHz bus When operated as an a...

Page 14: ...plete information is available for both devices from the manufacturer websites Table 2 Memory Address and Data Bus Pin Assignments Address signals Data signals ADDR0 NA ADDR8 H6 ADDR16 M5 DATA0 L1 DAT...

Page 15: ...nectors are labeled JA nearest the power jack JB JC and JD nearest the expansion connector Pinouts for the Pmod connectors are provided in the table below More than 30 low cost are available for attac...

Page 16: ...e FX2 Connector Pin Assignments J1A Name FPGA J1B Name FPGA 1 VCC3V3 1 SHIELD 2 VCC3V3 2 GND 3 TMS D15 3 TDO ROM 4 JTSEL 4 TCK A17 5 TDO FX2 5 GND 6 FX2 IO1 B4 6 GND 7 FX2 IO2 A4 7 GND 8 FX2 IO3 C3 8...

Page 17: ...e FAIL After the memory test the buttons and switches will drive the LEDs and seven segment display so that all user I O devices can be manually checked If the self test is not resident in the Platfor...

Page 18: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Digilent 410 134P KIT...

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