Digilent Nexys2 Reference Manual Download Page 11

Nexys2 Reference Manual 

 

Digilent 

www.digilentinc.com 

 

Copyright Digilent, Inc. 

  Page 11/17 

                                  Doc: 502-134 

 

from the cathodes, and those rays are fed by the current that flows into the cathodes. These particle 
rays are initially accelerated towards the grid, but they soon fall under the influence of the much larger 
electrostatic force that results from the entire phosphor-coated display surface of the CRT being 
charged to 20kV (or more). The rays are focused to a fine beam as they pass through the center of 
the grids, and then they accelerate to impact on the phosphor-coated display surface. The phosphor 
surface glows brightly at the impact point, and it continues to glow for several hundred microseconds 
after the beam is removed. The larger the current fed into the cathode, the brighter the phosphor will 
glow. 
 
Between the grid and the display surface, the beam passes through the neck of the CRT where two 
coils of wire produce orthogonal electromagnetic fields. Because cathode rays are composed of 
charged particles (electrons), they can be deflected by these magnetic fields. Current waveforms are 
passed through the coils to produce magnetic fields that interact with the cathode rays and cause 
them to transverse the display surface in a “raster” pattern, horizontally from left to right and vertically 
from top to bottom. As the cathode ray moves over the surface of the display, the current sent to the 
electron guns can be increased or decreased to change the brightness of the display at the cathode 
ray impact point. 
 
Information is only displayed when the beam is moving in the “forward” direction (left to right and top 
to bottom), and not during the time the beam is reset back to the left or top edge of the display. Much 
of the potential display time is therefore lost in “blanking” periods when the beam is reset and 
stabilized to begin a new horizontal or vertical display pass. The size of the beams, the frequency at 
which the beam can be traced across the display, and the frequency at which the electron beam can 
be modulated determine the display 
resolution. Modern VGA displays can 
accommodate different resolutions, 
and a VGA controller circuit dictates 
the resolution by producing timing 
signals to control the raster patterns. 
The controller must produce 
synchronizing pulses at 3.3V (or 5V) to 
set the frequency at which current 
flows through the deflection coils, and 
it must ensure that video data is 
applied to the electron guns at the 
correct time. Raster video displays 
define a number of “rows” that 
corresponds to the number of 
horizontal passes the cathode makes 
over the display area, and a number of 
“columns” that corresponds to an area 
on each row that is assigned to one 
“picture element” or pixel. Typical 
displays use from 240 to 1200 rows 
and from 320 to 1600 columns. The 
overall size of a display and the 
number of rows and columns 
determines the size of each pixel. 
 
Video data typically comes from a 
video refresh memory, with one or 

 

Current
waveform 
through 
horizontal 
defletion 
coil

Stable current ramp - information 
is displayed during this time

Retrace - no 
information 
displayed 
during this 
time

Total horizontal time

Horizontal display time

Horizontal sync signal 
sets retrace frequency

retrace 

time

time

HS

"back porch"

"front porch"

Display Surface

640 pixels per row are displayed
during forward beam trace

pixel 0,639

pixel 0,0

pixel 479,0

pixel 479,639

 

Figure 18: VGA system signals 

Summary of Contents for Nexys2

Page 1: ...nd a host of sensor and actuator interfaces All user accessible signals on the Nexys2 board are ESD and short circuit protected ensuring a long operating life in any environment The Nexys2 board is fu...

Page 2: ...ply and 100mA from the 3 3V supply Required current will increase if larger circuits are configured in the FPGA and if peripheral boards are attached The table above summarizes the power supply parame...

Page 3: ...e USB port A jumper on the Nexys2 board determines which source PC or ROM the FPGA will use to load its configuration The FPGA will automatically load a configuration from the Platform Flash ROM at po...

Page 4: ...udes a 50MHz oscillator and a socket for a second oscillator Clock signals from the oscillators connect to global clock input pins on the FPGA so they can drive the clock synthesizer blocks available...

Page 5: ...rent A ninth LED is provided as a power on LED and a tenth LED indicates FPGA programming status Note that LEDs 4 7 have different pin assignments due to pinout differences between the 500 and the 120...

Page 6: ...ter of the time but because the eye cannot perceive the darkening of a digit before it is illuminated again the digit appears continuously illuminated If the update or refresh rate is slowed to around...

Page 7: ...s 500mA and then activates a transistor switch to connect the USB cable voltage to the main input power bus The Nexys2 board typically draws around 300mA from the USB cable and care should be taken es...

Page 8: ...scan code When an extended key is released an E0 F0 key up code is sent followed by the scan code Scan codes for most keys are shown in the figure A host device can also send data to the keyboard Belo...

Page 9: ...period is 20 to 30KHz The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field and moving to the left generates a negative numbe...

Page 10: ...precise information or for information on other VGA frequencies refer to documentation available at the VESA website CRT based VGA displays use amplitude modulated moving electron beams or cathode ra...

Page 11: ...to right and top to bottom and not during the time the beam is reset back to the left or top edge of the display Much of the potential display time is therefore lost in blanking periods when the beam...

Page 12: ...erived Timings for sync pulse width and front and back porch intervals porch intervals are the pre and post sync pulse times during which information cannot be displayed are based on observations take...

Page 13: ...tatic DRAM device organized as 8Mbytes x 16bits It can operate as a typical asynchronous SRAM with read and write cycle times of 70ns or as a synchronous memory with an 80MHz bus When operated as an a...

Page 14: ...plete information is available for both devices from the manufacturer websites Table 2 Memory Address and Data Bus Pin Assignments Address signals Data signals ADDR0 NA ADDR8 H6 ADDR16 M5 DATA0 L1 DAT...

Page 15: ...nectors are labeled JA nearest the power jack JB JC and JD nearest the expansion connector Pinouts for the Pmod connectors are provided in the table below More than 30 low cost are available for attac...

Page 16: ...e FX2 Connector Pin Assignments J1A Name FPGA J1B Name FPGA 1 VCC3V3 1 SHIELD 2 VCC3V3 2 GND 3 TMS D15 3 TDO ROM 4 JTSEL 4 TCK A17 5 TDO FX2 5 GND 6 FX2 IO1 B4 6 GND 7 FX2 IO2 A4 7 GND 8 FX2 IO3 C3 8...

Page 17: ...e FAIL After the memory test the buttons and switches will drive the LEDs and seven segment display so that all user I O devices can be manually checked If the self test is not resident in the Platfor...

Page 18: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Digilent 410 134P KIT...

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