22.8.2018
Cmod S7 Reference Manual [Reference.Digilentinc]
https://reference.digilentinc.com/reference/programmable-logic/cmod-s7/reference-manual
6/12
FPGA Configuration files can be written to the Quad-SPI Flash (Macronix part number MX25L3233F). The FPGA will automatically
read a configuration file from this device at power on. A Spartan-7 25T configuration file requires 9,935,224 bits of memory, leaving
about 69% of the flash device (or ~2.8 MB ()) available for user data. A common use for this extra memory is to store MicroBlaze
programs too big to fit in the onboard block memory. These programs are then loaded and executed using a smaller bootloader program
that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into the bitstream, and then program the
bitstream and large MicroBlaze program into the Quad SPI Flash using Xilinx SDK.
The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is
outside the scope of this document. Xilinx's AXI Quad SPI IP core can be used to read/write the flash in a MicroBlaze design. Refer to
this core to learn more about using it, or to
(http://www.macronix.com/Lists/Datasheet/Attachments/6744/MX25L3233F,%203V,%2032Mb,%20v1.6.pdf)
for the flash device to learn how
to implement a custom controller. All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration and can be
used like any other FPGA I/O.
Figure 3.1 Flash Interface
The Cmod S7 includes a 12 MHz () crystal oscillator connected to pin M9 (an MRCC input on bank 14). This clock is intended to be
used as a general purpose system clock. The clock can drive MMCMs to generate clocks of various frequencies and with known phase
relationships that may be needed throughout a design. The 12 MHz () input clock cannot directly drive a PLL because they have a
minimum input frequency of 19 MHz (). Some rules restrict which MMCMs and PLLs may be driven by the 12 MHz () input clock. For a
full description of these rules and of the capabilities of the Spartan-7 clocking resources, refer to
(https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf)
, titled “7 Series FPGAs Clocking Resources User
Guide”.
Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will
properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The
wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user’s design.
The clocking wizard can be accessed from within the Vivado and IP Integrator tools.
Figure 4.1 Clock Input
3 Quad-SPI Flash
4 Oscillators/Clocks
