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Digilent 471-036, Hardware Reference Manual

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Digilent 471-036 Hardware Reference Manual Download Page 24

 

Figure 7.1: UART Connections

 

 

8. Zmod Ports

 

The Eclypse Z7 features two Zmod ports, which use SYZYGY Standard interfaces to 
communicate with installed SYZYGY pods. Both ports are compatible with version 1.1 
of the SYZYGY specification from Opal Kelly. 

SYZYGY SmartVIO functionality is implemented by the Eclypse's Platform MCU, as 
discussed in the 

1 Power Supplies

 section of this document. Each port's SYZYGY DNA 

is connected to both the Platform MCU and the Zynq's I2C 0 peripheral (MIO12:13) 
through a single I2C bus. Once the board is fully powered on, and the PMCU has 
configured itself in I2C slave mode, SYZYGY DNA data can be read directly from the 
pods, and the negotiated voltages and currents can be read from the PMCU over this 
bus. 

Warning

: 

SYZYGY pods are NOT hot-swappable. Connecting or disconnecting a pod 

from the Eclypse while the board is powered on may cause damage to the pod and/or 
the board, and is to be avoided.

 

Each SYZYGY Standard interface contains 16 single-ended I/O pins, 8 differential I/O 
pairs (which can alternatively be used as 16 additional single-ended I/O pins), and two 
dedicated differential clocks - one for input and one for output. Each Zmod port has a 
I/O bank of the Zynq dedicated to it, which is powered by a dedicated adjustable rail, 
configured by the Platform MCU as the Eclypse is powered on. Template constraints for 
each Zmod port can be found in the Eclypse Z7's Master XDC file, available through 
Digilent's 

digilent-xdc

 repository on Github. 

Digilent provides Eclypse-compatible low-level IPs, scripted Vivado flows, and software 
libraries to support each 

Digilent Zmod

. 

For more information on the SYZYGY standard, see 

syzygyfpga.io

. 

Summary of Contents for 471-036

Page 1: ...ially including software defined radio ultrasound other medical devices and much more As a host board for Zmods applications for the Eclypse can vary significantly between system configurations Petalinux is supported out of the box Pre built Linux images are accompanied by a software API for bulk data transfer This system allows new users to get started without touching hardware until desired The ...

Page 2: ... 12V 5A supply o Platform MCU for configuration of adjustable power supplies and temperature management USB and Ethernet o Gigabit Ethernet PHY o USB JTAG programming circuitry o USB UART bridge o USB micro AB port with USB 2 0 PHY with Host Device OTG capabilities Zmod Ports o 2 ports following the SYZYGY Standard interface specification o Compatible with a variety of SYZYGY pods allowing for a w...

Page 3: ...rside of board 2 Header for Case Power Switch 8 Pmod Ports 14 microSD Card Slot 3 Power Switch 9 User Buttons and LEDs 15 USB JTAG UART Port 4 FPGA Fan Header 10 DDR3L Memory 16 Ethernet Port 5 Zynq 7000 SoC and FPGA Fan 11 Case Fan Header 17 USB AB Host Device OTG Port 6 External JTAG Port 12 Programming Mode Select Jumper 18 Power Supply Connector ...

Page 4: ... targeting custom Petalinux projects including support for each Digilent Zmod for high speed I O capabilities The Eclypse Z7 is fully compatible with Xilinx s high performance Vivado Design Suite This tool set melds FPGA logic design and embedded ARM software development into an easy to use intuitive design flow It can be used for designing systems of any complexity from a complete operating syste...

Page 5: ... Processing Unit APU which includes 2 Cortex A9 processors Advanced Microcontroller Bus Architecture AMBA Interconnect DDR3 Memory controller and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins called Multiplexed I O or MIO pins Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I O through th...

Page 6: ...nents connected to the MIO pins of the Eclypse Z7 The Vivado board files found on the Eclypse Z7 Resource Center can be used to properly configure the PS to work with these peripherals It is also possible to use the example projects found on the resource center as a starting point for custom designs MIO 0 15 Bank 500 MIO 500 3 3 V Peripherals Pin GPIO SPI Flash ENET 0 SYZYGY UART 0 0 N C 1 CS 2 DQ...

Page 7: ...9 Ethernet Reset 10 N A 11 N A 12 DNA SCL I2C 0 13 DNA SDA I2C 0 14 UART Input 15 UART Output MIO 16 53 Bank 501 MIO 501 1 8V Peripherals Pin ENET 0 USB 0 SD 0 16 TXCK 17 TXD0 18 TXD1 19 TXD2 20 TXD3 ...

Page 8: ...21 TXCTL 22 RXCK 23 RXD0 24 RXD1 25 RXD2 26 RXD3 27 RXCTL 28 DATA4 29 DIR 30 STP 31 NXT 32 DATA0 33 DATA1 34 DATA2 ...

Page 9: ...35 DATA3 36 CLK 37 DATA5 38 DATA6 39 DATA7 40 CCLK 41 CMD 42 D0 43 D1 44 D2 45 D3 46 USB Reset 47 CD 48 Ethernet Interrupt GPIO ...

Page 10: ...pplies The Eclypse Z7 power circuitry was carefully designed to meet the requirements of the Zynq 7000 and all peripherals while providing the flexibility needed to power a variety of different configurations of Zmod SYZYGY modules An overview of the power circuit is shown in Figure 1 1 ...

Page 11: ...nnector J11 The supply must use a center positive 2 1 mm internal diameter plug and deliver between 11 5V and 12 5V DC It should also be able to provide at least 5 A 60 Watts in order to support power hungry Zynq projects and external peripherals A compatible power supply ships with the Eclypse Z7 Table 1 1 1 Eclypse Z7 Power Input Specifications Connector Type Connector Label Schematic Net Name M...

Page 12: ... microSD VCC4V3 VCC5V0 LDO IC26 4 3V 5 0 3A Pmods VADJA VIN12V0 Buck IC27 1 2V to 3 3V 5 1 8A FPGA Zmod Port A VADJB VIN12V0 Buck IC27 1 2V to 3 3V 5 1 8A FPGA Zmod Port B VADJC VIN12V0 Buck IC25 2 5 to 5 5V 5 0 3A FPGA Fan The power budget of VCC5V0 is shared by the SYZYGY ports USB OTG VBUS RGB LEDs and Case Fan As such the actual maximum current achievable by each peripheral varies with the Ecl...

Page 13: ...LEDs 124 8 USB OTG VBUS 500 Zmod Port A 1000 Zmod Port B 1000 Case Fan 250 The two SYZYGY ports share a budget of 2A from the 3 3V supply The two Pmod ports share a budget of 0 5A which is allocated to the SYZYGY ports if no Pmods are installed Due to the requirements of the custom power sequencer IC29 Digilent recommends that peripheral modules Pmods and Zmods attached to and powered by the Eclyp...

Page 14: ...p sequence is as follows 1 VCC5V0 FAN5V0 2 VCC1V0 3 VCC1V8 4 DDR1V35 DDRVTT 5 VCC3V3 6 VCC4V3 7 VADJA VADJB VADJC The sequencer is provided 3 3V power by a dedicated regulator a Texas Instruments LP2985 IC28 The sequencer ensures that the supply rails follow the Xilinx recommended start up and shut down sequences Note VADJA VADJB and VADJC are controlled by the Platform MCU PMCU and may or may not...

Page 15: ...rred to as the Platform MCU PMCU to implement the SmartVIO requirements of the SYZYGY standard as well as to monitor the Zynq die temperature and to control the Eclypse s fan When the Eclypse is turned on the PMCU enumerates the pods attached to the Eclypse s SYZYGY ports and retrieves their DNA in order to correctly configure the variable supplies After SYZYGY enumeration is complete the PMCU con...

Page 16: ...es Optional Features Supported DDRVCCSEL Control No INIT_B Control No USB Hub Support No Table 1 6 3 Supported Platform MCU Fan COntrol Features Feature FAN_1 FPGA Fan FAN_2 Case Fan Enable Disable Yes No Fixed Speed Control Yes No Automatic Speed Control Yes No RPM Measurement Yes if supported by installed fan 1 Yes if supported by installed fan 2 ...

Page 17: ... attached to JP5 on the Eclypse Z7 If the BootROM is being executed due to a reset event then the mode pins are not latched and the previous state of the mode register is used This means that the Eclypse Z7 needs a power cycle to register any change in the programming mode jumper JP5 Next the BootROM copies an FSBL from the form of non volatile memory specified by the mode register to the 256 KB o...

Page 18: ...to connector J4 labeled SD CARD The following procedure will allow you to boot the Zynq from microSD with a standard Zynq Boot Image created with the Xilinx tools 1 Format the microSD card with a FAT32 file system 2 Copy the Zynq Boot Image created with Xilinx SDK to the microSD card 3 Rename the Zynq Boot Image on the microSD card to BOOT bin 4 Eject the microSD card from your computer and insert...

Page 19: ...use the PS to not be accessible from the onboard JTAG circuitry and only the PL will be visible in the scan chain To access the PS over JTAG while in independent JTAG mode users will have to route the signals for the PJTAG peripheral over EMIO and use an external device to communicate with it 3 DDR3L Memory The Eclypse Z7 includes two Micron MT41K256M16TW 107 DDR3L memory components creating a sin...

Page 20: ...CB trace length reports The DQS to CLK Delay and Board Delay values are calculated specific to the Eclypse Z7 memory interface PCB design For more details on memory controller operation refer to the Xilinx Zynq Technical Reference manual 4 Quad SPI Flash The Eclypse Z7 features a Spansion S25FL128S 4 bit Quad SPI serial NOR flash The key device attributes are Part number S25FL128S 16 MB of memory ...

Page 21: ...t which is used to generate the clocks for each of the PS subsystems The 33 3333 MHz input allows the processor to operate at a maximum frequency of 667 MHz and the DDR3 memory controller to operate at a maximum clock rate of 533 MHz 1066 MT s The Eclypse Z7 board files available on the Eclypse Z7 Resource Center will automatically configure the Zynq processing system IP core in Vivado to work wit...

Page 22: ...Ethernet PHY is held in hardware reset by driving the PHYRSTB signal low Figure 5 1 Eclypse Z7 clocking 6 Reset Sources The Eclypse Z7 provides several different methods of resetting the Zynq 7000 device as described in the following sections 6 1 Power on Reset The Zynq PS supports external power on reset signals The power on reset is the master reset of the entire chip This signal resets every re...

Page 23: ... data traffic on the Zynq pins The port is tied to PS MIO pins and can be used in combination with the UART 0 controller The Zynq presets file available in the Eclypse Z7 Resource Center takes care of mapping the correct MIO pins to the UART 0 controller and uses the following default protocol parameters 115200 baud rate 1 stop bit no parity 8 bit character length Two status LEDs provide visual fe...

Page 24: ...us Warning SYZYGY pods are NOT hot swappable Connecting or disconnecting a pod from the Eclypse while the board is powered on may cause damage to the pod and or the board and is to be avoided Each SYZYGY Standard interface contains 16 single ended I O pins 8 differential I O pairs which can alternatively be used as 16 additional single ended I O pins and two dedicated differential clocks one for i...

Page 25: ...th USB VBUS output Case Fan and RGB LEDs Total 3 3V Supply Current 2 0 A Shared VIO Supply Voltage Range 1 2V to 3 3V 1 2V to 3 3V Total VIO Supply Current 1 8A VIO Group 1 1 8A VIO Group 2 Port Groups Group 1 A Group 2 B I O Count 28 total 8 DP 28 total 8 DP Length Matching 73 7 mm 0 2 mm including Zynq package delay 9 microSD Slot The Eclypse Z7 provides a microSD slot J4 for non volatile extern...

Page 26: ... MIO42 7 SD_D1 Data 1 MIO43 8 SD_D2 Data 2 MIO44 1 SD_D3 Data 3 MIO45 2 SD_CCLK Clock MIO40 5 SD_CMD Command MIO41 3 SD_CD Card Detect MIO47 9 The SD slot is powered from 3 3V but is connected through MIO Bank 1 501 1 8V Therefore a TI TXS02612 level shifter performs this translation The TXS02612 is actually a 2 port SDIO port expander but only its level shifter function is used The connection dia...

Page 27: ...ted accessed like a standard block device typically with a device node named dev mmcblk0 See the Petalinux and Xilinx SDK documentation for more information 10 USB Micro AB Device Host OTG Port The Eclypse Z7 implements one of the two available PS USB OTG interfaces on the Zynq device A Microchip USB3320 USB 2 0 Transceiver Chip with an 8 bit ULPI interface is used as the PHY The PHY features a co...

Page 28: ...ore information Table 10 1 USB Mode Jumper Positions Mode JP1 Shorted JP2 Shorted Embedded Host No Yes General Purpose Host Yes Yes Peripheral Device No No 11 Ethernet The Eclypse Z7 uses a Realtek RTL8211E VL PHY to implement a 10 100 1000 Ethernet port for network connection The PHY connects to MIO Bank 501 1 8V and interfaces to the Zynq 7000 AP SoC via RGMII for data and MDIO for management Th...

Page 29: ...icate traffic J3 LD2 right side of connector and valid link state J3 LD1 left side of connector Table 11 1 shows the default behavior Table 11 1 Ethernet status LEDs Function Designator State Description LINK J3 LD1 Steady on Link 10 100 1000 Blinking 0 4s ON 2s OFF Link Energy Efficient Ethernet EEE mode ...

Page 30: ...erting a 2ns delay on both the TXC and RXC so that board traces do not need to be made longer On an Ethernet network each node needs a unique MAC address To this end the one time programmable OTP region of the Quad SPI flash has been programmed at the factory with a 48 bit globally unique EUI 48 64 compatible identifier The OTP address range 0x20 0x25 contains the identifier with the first byte in...

Page 31: ...e driven by the Zynq PL through a transistor which inverts the signals Therefore to light up the tri color LED the corresponding PL pins need to be driven high The tri color LED will emit a color dependent on the combination of internal LEDs that are currently being illuminated For example if the red and blue signals are driven high and green is driven low the tri color LED will emit a purple colo...

Page 32: ...A s motor drivers sensors and other functions See www digilentinc com for more information The vivado library and vivado hierarchies repositories on the Digilent Github contains pre made IP cores for many of these Pmods that greatly reduces the work of integrating them into your project See the Pmod related tutorials on the Eclypse Z7 Resource Center for help using them The Eclypse Z7 s two Pmod p...

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