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Zeta User Manual Rev 1.0
Page 50
14.7
Interrupt Operation
14.7.1
Overview
Interrupts provide a means for a circuit to request service from the processor autonomously without requiring
the application software to continuously poll the circuit. When the circuit requires attention, it generates an
interrupt request signal to the processor. The processor responds by passing program control to a dedicated
software routine, which provides the functionality required by the circuit.
The maximum interrupt rate is not a fixed value but varies with the operating system and the duration that the
interrupt service routine runs. The maximum rate must be determined by trial and error. However, a general
guideline is that for Linux and Windows the rate should not exceed 1KHz. Because all interrupts require some
processing overhead, the lower the rate the better. However, in the case of A/D sampling, a slower interrupt rate
also delays the availability of new data. The programmer must find the ideal balance between processor load and
response time.
The primary host interface for the Zeta base board
“A” model data acquisition circuit is the SPI bus.
However, the
SPI bus does not provide a means to support interrupt operation. Therefore, Zeta base board
“A” m
odels provide
the ability to generate interrupts on the ISA bus.
The ISA interrupt level, or IRQ number, can be chosen from among IRQ 5 and 7. The chosen interrupt level is
dedicated to the data acquisition circuit and cannot be shared with other add-on PC/104 boards. The Zeta board
BIOS provides support for up to 4 other IRQs for PC/104 boards. These IRQs are configured in the BIOS setup
screens.
14.7.2
Interrupt Sources
Interrupts can come from several sources in the data acquisition circuit. A status register is used to indicate which
circuit or circuits are requesting interrupt service, so the application software can respond accordingly.
A/D converter: For high speed sampling, the data acquisition circuit supports the use of interrupts to pass data
back to the processor in large blocks instead of one sample at a time. This greatly reduces the processor time
required to handle the data flow. A programmable FIFO holds the A/D data and generates an interrupt request
when the number of samples in the FIFO reaches a user-specified threshold. This is described more fully in the
data acquisition section above.
Counter/timers: Counters 2 and 3 can be used to generate interrupts at programmable frequencies. Generally,
only one or the other counter is used for interrupts, however it is possible to use both simultaneously.
Edge detection circuit: As described above, digital I/O port B can be used to monitor the state of up to 8 digital
inputs and generate an interrupt request when a specific transition is seen on any of its 8 inputs.
