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Zeta User Manual Rev 1.0
Page 39
activity such as a rotary or linear encoder. Clock timing is used for high speed sampling or where the time between
samples must be precise.
A channel sequencer circuit in the FPGA controls which channels sampled by the ADC. The sequencer can be
programmed to select any single channel repeatedly, or it can be programmed to select any consecutive group of
channels. As described above, the A/D front end consists of two 8-channel multiplexors connected to two analog
inputs of the ADC. In single-ended mode, the channel sequencer will treat the 16 inputs as channels 0-15 with
reference to analog ground, and in differential mode the sequencer will treat them as 8 differential channels, with
channels 0-7 forming the high side of the inputs (renamed as channels 0+ to 7+) and channels 8-15 forming the
low side of the inputs (renamed as channels 0- to 7-).
The sequencer works in conjunction with two available sampling modes called sample and scan. In sample mode,
each A/D clock or trigger event causes one A/D conversion to occur. If the sequencer is programmed for a single
channel, each successive A/D conversion will sample the same channel. This method is useful for high speed
sampling of an AC signal. If the sequencer is programmed for a range of channels, then each successive A/D clock
will cause the next channel in the selected range to be sampled, with the result that all the selected input channels
are sampled one at a time in round robin fashion.
In scan mode, each A/D clock generates one A/D conversion on all channels selected by the sequencer (called the
scan range) in tight succession. This method is typically used with the programmable clock circuit to measure a
group of channels all at once. The number of selected channels is called the scan size. The timing of scan mode
differs significantly from sample mode in that all selected channels are sampled as closely together as possible in
time instead of being spread out equally in time as is done in sample mode. The analog input circuit does not
support simultaneous sampling mode, where all inputs are sampled at exactly the same time.
One very important fact to remember is that because scan sampling generates one A/D conversion for every
channel in the scan range, the total sample rate of the circuit is equal to the clock rate times the scan size. This
total sample rate must be kept at or below the hard 100KHz limit of the A/D converter.
A second very important fact is that the fastest possible sample rate for any channel is 100KHz divided by the scan
size in scan mode or the number of selected channels in sample mode. Thus it is not possible to sample more than
one channel at 100KHz. If two channels are selected, the maximum sample rate for each channel is 50KHz, and so
on.
14.2.3
A/D FIFO and High Speed Sampling
The FPGA contains a 2048 sample FIFO which supports high-speed A/D sampling. The FIFO enables the CPU to
avoid having to respond every time an A/D conversion occurs, which would consume too much processor time
when high speed sampling is being executed. Instead, the A/D samples are stored in the FIFO, and when the
number of samples reaches a user-defined threshold, an interrupt occurs on the ISA bus. The software can then
respond to the interrupt and read out a large number of samples all at once.
The Diamond Systems Universal Driver software provides full support for high speed A/D sampling with FIFO and
interrupt support. Please refer to that user manual for operating details. When using Universal Driver software,
the interrupt rate is equal to the total A/D sample rate divided by the programmed FIFO threshold, because each
time the interrupt service routine runs, it will read out the number of samples equal to the threshold value. The
threshold is programmable so that the application software can optimize the interrupt rate for its needs. In general
the interrupt rate should not exceed 1KHz, and in most cases an interrupt rate of 100-200Hz is recommended.
