UM-B-077
DA14681 Wearable Development Kit Hardware Manual
User Manual
Revision 1.2
06-Apr-2017
CFR0012
10 of 47
© 2017 Dialog Semiconductor
V33:
Output voltage rail (3.3 V). A ceramic decoupling capacitor of 4.7
F (C3), (0402 package,
6.3 V) is placed. V33 cannot be turned off.
SIMO DC-DC converter outputs:
V18, V18P, V12, V14. The inductor needed for DC-DC operation
is placed externally. A low DCR inductor (L1) of 470 nH, 0805 is connected on LX/ LY pins.
V18, V18P:
Power rails (1.8 V) for supplying external devices, even when the system is in sleep
mode. Decoupling ceramic capacitors (C4, C5) of 10
F (0603 package, 16 V), are placed as close
as possible to the V18, V18P pins. V18 is assigned to the external Flash memory. The current
delivery capability of the V18, V18P power rails in active mode is 75 mA, whereas in sleep mode it is
2 mA. When in sleep mode the 1.8 V is supplied directly from the LDO, while in active mode from a
DC-DC converter.
V12:
Power rail that supplies the digital core of the DA14681 and delivers up to 50 mA at 1.2 V when
in active mode. A 4.7
F decoupling capacitor (C6) is used (0402 package, 6.3 V).
V14:
Power rail that delivers up to 20 mA at 1.4 V and should
not
be used for supplying external
devices. A 4.7
F decoupling capacitor (C7) is placed close to the V14 pin (0402 package, 6.3 V).
V14_RF:
Supply voltage input. It is shorted to V14 on the PCB layout. V14_RF powers the RF
circuits via a number of dedicated internal LDOs. A 4.7
F decoupling capacitor (C8) is placed as
close to the V14_RF pin as possible.
VDDIO:
QSPI Flash interface supply voltage. It is connected to the same power rail as the Flash
memory. A 1
F decoupling capacitor (C1) is added. (0402 package, 6.3 V).
4.1.1
Debugging Section
The DA14681 wearable reference design has a dedicated debugging port as shown in
Figure 3.
Two
debugging ports, JTAG and UART are used on the DA14681 SoC.
The USB-to-JTAG and USB-to-UART functions are implemented by an external Communication
Interface Board (CIB) as shown in
Figure 5
. This interface board has a SEGGER chip running the
JLink-OB firmware.
Figure 5: Communication Interface Board (CIB)
