dg_nvmeg4ip_instruction_xilinx_en.doc
20-Apr-20
Page 1
NVMe IP with PCIe Gen4 Soft IP demo instruction
Rev1.1
20-Apr-20
This document describes the instruction to run NVMeG4-IP demo on FPGA development board
by using the PCIe adapter board, AB18-PCIeX16 board. The demo is designed to write and verify
data with NVMe Gen4 SSD. User controls the test operation through Serial console.
1 Environment Requirement
To run the demo on FPGA development board, please prepare following environment.
1) Supported FPGA Development board: VCU118
2) PC installing Xilinx programmer software (Vivado) and Serial console software such as
TeraTerm
3) AB18-PCIeX16 board, provided by Design Gateway.
https://dgway.com/ABseries_E.html
4) ATX power supply for AB18.
5) Xilinx power adapter for FPGA board
6) PCIe Gen4 NVMe SSD
7) Two micro USB cables for programming FPGA and Serial console, connecting between
FPGA board and PC
