53
Appendix E
System Overview
DMA Controller 1
Ch0-Reserved for User
Ch1-Reserved for User
Ch2-Diskette
Ch3-Reserved for User
DMA Controller 2
Ch4-Cascade for CTRL 1
Ch5-Reserved for User
Ch6-Reserved for User
Ch7-Reserved for User
Note:
DMA controller 1 supports 8-bit data transfer.
DMA controller 2 supports 16-bit data transfer.
Address Generation for DMA Channels 3 to 0
Source
DMA Page Memory
DMA Controller 1
Address
A23
↔
A16
A15
↔
A0
Address Generation for DMA Channels 7 to 5
Source
DMA Page Memory
DMA Controller 2
Address
A23
↔
A17
A16
↔
A1
Page Memory Address
I/O Port Address
0081H
0082H
0083H
0087H
0089H
008AH
008BH
Page Memory
DMA Channel 2
DMA Channel 3
DMA Channel 1
DMA Channel 0
DMA Channel 6
DMA Channel 7
DMA Channel 5
