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Award BIOS Setup Utility
CPU to PCI Write Buffer
Enabled
Writes from the CPU to the PCI bus are buffered to
offset the speed difference between the CPU and PCI
bus.
Disabled
Writes are not buffered therefore the CPU must wait
until the write cycle is complete before starting another
write cycle.
PCI Dynamic Bursting
When enabled, every write transaction goes to the write buffer.
PCI Master 0 WS Write
When enabled, writes to the PCI bus are executed with zero wait
state.
PCI Delay Transaction
When enabled, this function frees up the PCI bus for other PCI
masters during the PCI-to-ISA transactions. This allows PCI and ISA
buses to be used more efficiently and prevents degradation of
performance on the PCI bus when ISA accesses are made.
PCI#2 Access #1 Retry
Set this field to Enabled if you want to rotate the priority of the PCI
masters.
AGP Master 1 WS Write
Set this field to Enabled to add one clock tick to AGP write
operations.
AGP Master 1 WS Read
Set this field to Enabled to add one clock tick to AGP read
operations.
Memory Parity/ECC Check
If you are using
x72 (72-bit) PC SDRAM DIMMs, which are DIMMs
that support the ECC (Error Checking and Correction) function, set
this field to Enabled.
