Denon DVP-602CI, Service Manual

Page: 27 / 87

27
DVP-602CI
17 P83/INT1 ACKSIMO I - E ↓ &L - Ed Z MAIN-SUB μcom comm. Control input pin
18 P82/INT0 SUB BDOWN I - E ↓ &L Eu Z Power down detect (Power down : L)
19 P81 IP RST O C - - Ed Z IP CONV(Realta) reset
20 P80 GUI WRITE O - - - - Z GUI ROM rewrite control(ACTIVE"L")
21 P77 PLDTDI̲A O C - - - Z PLD rewrite control(JTAG), OPEN other than communication time
22 P76 APLDCS O C - - Eu Z AUDIO PLD control pin
23 P75 APLDSO O C - - Eu Z AUDIO PLD control pin
24 P74 APLDCLK O C - - Eu Z AUDIO PLD control pin
25 P73/CTS2 DSD ON O C - - Ed Z DSD signal input : H
26 P72/CLK2 REALTAMODE O C - - Ed Z REALTA rewrite control pin
27 P71/RXD2 VSCL I/O C - - Eu Z
VIDEO I2C- IP CONV(Realta)/V̲DECODER(ADV7403)/GUI̲FPGA
control pin
28 P70/TXD2 VSDA I/O C - - Eu Z
VIDEO I2C- IP CONV(Realta)/V̲DECODER(ADV7403)/GUI̲FPGA
control pin
29 P67/TXD1 TXD O C - - Eu Z Data transmission output to outside/REALTA rewrite control pin
30 P66/RXD1 RXD I - Lv - Eu Z Data receive input from outside/REALTA rewrite control pin
31 P65/CLK1 O - - - Ed Z Not used
32 P64/CTS1 CEC̲OUT O C - - Eu Z CEC-D signal output pin(SII9185)
33 P63/TXD0 SOMI O C - - - Z MAIN-SUB μcom comm. control pin
34 P62/RXD0 SIMO I - - - Ed Z MAIN-SUB μcom comm. control pin
35 P61/CLK0 CLKSIMO I - - - Ed Z MAIN-SUB μcom comm. control pin
36 P60/CTS0 REQSOMI O C - - Ed Z MAIN-SUB μcom comm. control pin
37 P57 O C - - Ed Z Not used
38 P56 O C - - Ed Z Not used
39 P55/EPM I/O - Lv - Ed Z Not used
40 P54 VSEL CLK O C - - - Z GUI built-in VIDEO SW control pin
41 P53 VSEL DATA O C - - - Z GUI built-in VIDEO SW control pin
42 P52 VSEL C1 O C - - - Z GUI built-in VIDEO SW control pin
43 P51 VSEL C2 O C - - - Z GUI built-in VIDEO SW control pin
44 P50/CE
CECSEL/(FRASHCE)/DSP
BOOT
I/O - - - Eu Z
CEC output LINE switching(LINE1 fix)/(Rewrite boot : H input/DSP
boot control(Rewrite boot : L input)
45 P47 REALTAWRITE O C - - Eu Z REALTA rewrite : L,Other : H
46 P46 (DSP2POWER) O - - - - Z Not used
47 P45 HS INT2 I - E ↓ &L - Eu Z HDMI IN SEL2(SiI9185) INT output
48 P44 HS INT1 I - E ↓ &L - Eu Z HDMI IN SEL1(SiI9185) INT output
49 P43 HDMI R INT I - E ↓ &L - - Z HDMI RECEIVER(SiI9035)INT output
50 P42 HSCL/EDIT SCL I/O C - - Eu Z VIDEO I2C/HDMI EDIT(E2PROM) control pin
51 P41 HSDA/EDIT SDA I/O C - - Eu Z VIDEO I2C/HDMI EDIT(E2PROM) control pin
52 P40 TMDS SWITCHER 1 RST O C - - Ed Z TMDS SWITCHER HDMI IN SEL(SiI9185) reset
53 P37 HDMI R RST O C - - Ed Z HDMI RECEIVER(SiI9135) reset
54 P36 HDMI T1 RST O C - - Ed Z HDMI TRANSMITTER1 (SiI9134) reset
55 P35 HDMI T2 RST O C - - Ed Z HDMI TRANSMITTER2 (SiI9134) reset
56 P34 HDMI T1 INT I - Lv - . Z HDMI OUT signal detect input(HDMI TRANS1 SiI9134)
57 P33 HDMI T2 INT I - Lv - - Z HDMI OUT signal detect input(HDMI TRANS2 SiI9134)
58 P32 TMDS SWITCHER 2 RST O C - - Ed Z TMDS SWITCHER HDMI IN SEL2(SiI9185) reset
59 P31 HPD6 O C - - - Z HDMI IN6 pin, HP DET control pin ( "H"enable ，"L"disable )
60 VCC VCC - - - - - - +3.3V
61 P30 HPD5 O C - - - Z HDMI IN5 pin, HP DET control pin ( "H"enable ，"L"disable )
62 VSS VSS - - - - - - GND
63 P27 HPD4 O C - - - Z HDMI IN4 pin, HP DET control pin ( "H"enable ，"L"disable )
64 P26 HPD3 O C - - - Z HDMI IN3 pin, HP DET control pin ( "H"enable ，"L"disable )
65 P25 HPD2 O C - - - Z HDMI IN2 pin, HP DET control pin ( "H"enable ，"L"disable )
66 P24 HPD1 O C - - - Z HDMI IN1 pin, HP DET control pin ( "H"enable ，"L"disable )
67 P23 COMPINRL O C - - - Z COMPONENT1(RCA) : L，COMPONENT2(BNC) : H
68 P22 E̲COMPRL O C - - - Z Not used (Fixed to L)
69 P21 CVBSRL O C - - - Z Not used (Fixed to L)
70 P20 P.SAVE O C - - - Z COMPONENT1or2 : H，Ohter : L(mute)
71 P17/INT5 SRL O C - - - Z Not used (Fixed to L)
72 P16/INT4 COMPSIGDET I - - - Eu Z L:No signal、H:Signal
73 P15/INT3 VSIGDET I - - - Eu Z L:No signal、H:Signal
74 P14/D12 SSIGDET I - - - Eu Z L:No signal、H:Signal
75 P13/D11 SUBnCE O C - - Ed Z FPGA rewrite control(MAIN FPGA&GUI FPGA combined use)
Pin Pin Name Symbol I/O Type Det Op(Int.) Op(Ext.) Res Function