Denon DVM-4800, Service Manual

Page: 30 / 106

30
DVM-4800
DXP7001AF (IC201)
1 11
12
22
23 33
34
44
DXP7001AF Terminal Function
Pin
No.
Pin Name I/O Description
1 MDT Ip Microcomputer Interface Data
2 MCK Ip Microcomputer Interface Clock
3 MLEN Ip Microcomputer Interface Latch Enable
4 RSTN Ip Reset Terminal
5 DLRCK Ip Audio Serial Input Data L/R Clock
6 VSS
−
Ground Terminal
7 DBCK Ip Audio Serial Input Bit Clock
8 DDT Ip Audio Serial Input Data
9 TEST2N Ip
Test Setting Terminal 2 (Alpha-processor 1
Output shifts 12-bit.)
10 TEST3N Ip
Test Setting Terminal 3 (Alpha-processor 2
Output stops.)
11 TEST4N Ip
Test Setting Terminal 4 (Lambda-processor
Output stops.)
12 DFBCK Ip Lambda-processor Input Bit Clock
13 DFWCK Ip Lambda-processor Input Word Clock
14 DOL Ip Lambda-processor Input Data L-channel
15 DOR Ip Lambda-processor Input Data R-channel
16 LMOD Ip Lambda-processor Operation Mode Set
17 OMOD1 Ip Output Mode Setting Terminal 1
18 OMOD2 Ip
Output Mode Setting Terminal 2
19 INVIN Ip
Lambda-processor Input Reversed
Polarity Terminal
20 BCKO O Lambda-processor Output Bit Clock
21 WCKO O Lambda-processor Output Word Clock
22 WCKO2 O
Lambda-processor Output Word Clock 2
(for Canceling OFFSET on 1DAC
Pin
No.
Pin Name I/O Description
23
−
P24L O
−
/Lambda-processor Lch 24
th
bit Output *1, *2
24
−
P23L O
−
/Lambda-processor Lch 23
rd
bit Output *1, *2
25
−
P22L O
−
/Lambda-processor Lch 22
nd
bit Output *1, *2
26
−
P21L O
−
/Lambda-processor Lch 21
st
bit Output *1
27
−
P20L O
−
/Lambda-processor Lch 20
th
bit Output *1
28 VDD
−
Power Supply Terminal
29 SO2L/P19L O
Lambda-processor Lch(
−
) Output /19
th
bit
Output *1
30 SO1L O Lambda-processor Lch(+) Output
31 SO1R O Lambda-processor Rch(+) Output
32 SO2R/P19R O
Lambda-processor Rch(
−
) Output/19
th
bit
Output *1
33
−
P20R O
−
/Lambda-processor Rch 20
th
bit Output *1
34
−
P21R O
−
/Lambda-processor Rch 21
st
bit Output *1, *2
35
−
P22R O
−
/Lambda-processor Rch 22
nd
bit Output *1, *2
36
−
P23R O
−
/Lambda-processor Rch 23
rd
bit Output *1, *2
37
−
P24R O
−
/Lambda-processor Rch 24
th
bit Output *1, *2
38 TEST1N Ip Test Terminal 1 (Alpha-processor 1 stops)
39 CKSLN Ip System Clock Select (384fs system /
256fs system)
40 CKDV1 Ip System Clock Divider Select Terminal 1
41 CKDV2 Ip
System Clock Divider Select Terminal 2
42 XTI I X-TAL Oscillator Input Terminal
43 XTO O X-TAL Oscillator Output Terminal
44 CKO O Clock Output Terminal
(Ip = Input Terminal with pull-up)
*1: Outputted on OMOD1=L (18-bit Alternate Output or 20
-
bit Parallel Output)
*2: Internal Signal is outputted on OMOD1=H (24-bit Alternate Output or 24
-
bit Parallel Output) and one of TEST1N, TEST2N, TEST3N
or TEST4N is set to L.
OMOD1
L H
L
18bit
Alternate
24bit
Alternate
OMOD2
H
20bit
Parallel
24bit
Parallel
CKDV1
L H
192fs (CKSLN=H)
L
256fs (CKSLN=H)
768fs
192fs (CKSLN=H)
CKDV2
H
256fs (CKSLN=H)
384fs