Denon DN-X1500, Service Manual, Page: 15 / 60

15
15
DN-X1500
PCM1791A (IC402)
1
2
3
4
5
6
7
8
9
10
11
12
13
14 28
27
26
25
24
23
22
21
20
19
18
17
16
15
LRCK
BCK
DATA
MUTE
SCK
RST
V
DD
DGND
AGNDF
V
CC
R
AGNDR
V
OUT
R–
V
OUT
R+
V
COM
MS
MC
MDI
MDO
MSEL
ZEROL
ZEROR
V
CC
F
V
CC
L
AGNDL
V
OUT
L–
V
OUT
L+
AGNDC
V
CC
C
(TOP VIEW)
FUNCTIONAL BLOCK DIAGRAM
Power Supply
RST
SCK
Advanced
Segment
DAC
Modulator
VOUTL+
VOUTL–
Bias
and
Vref
V
CC
F
V
DD
AGNDR
V
CC
R
AGNDL AGNDF
D/S and Filter
8
Oversampling
Digital
Filter
and
Function
Control
Audio
Data Input
I/F
LRCK
BCK
DATA
MDO
MDI
MC
MS
AGNDC
V
CC
C
DGND
Current
Segment
DAC
and
I/V Buffer
VCOM
Function
Control
I/F
Zero
Detect
ZEROL
ZEROR
System
Clock
Manager
MSEL
MUTE
V
CC
L
VOUTR–
VOUTR+
D/S and Filter
Current
Segment
DAC
and
I/V Buffer
Terminal Functions
TERMINAL
I/O DESCRIPTIONS
NAME PIN
I/O DESCRIPTIONS
AGNDC 16 – Analog ground (internal bias and current DAC)
AGNDF 9 – Analog ground (DACFF)
AGNDL 19 – Analog ground (L-channel I/V)
AGNDR 11 – Analog ground (R-channel I/V)
BCK 2 I Bit clock input. Connected to GND for DSD mode (1)
DATA 3 I Serial audio data input for normal operation. L-channel audio data input for external DF and DSD
modes (1)
DGND 8 – Digital ground
LRCK 1 I Left and right clock (fS) input for normal operation. WDCK clock input in external DF mode.
R-channel audio data for DSD mode (1)
MC 27 I Shift clock for function control register (1)
MDI 26 I/O Serial data input for function control register (2)
MDO 25 O Serial data output for function control register (3)
MS 28 I/O Mode control chip select and latch signal (4)
MSEL 24 I I2C/SPI select (1)
MUTE 4 I Analog output mute control for normal operation. R-channel audio data input for external DF mode (1)
RST 6 I Reset (1)
SCK 5 I System clock input. BCK (64 fS) clock input for DSD mode (1)
VCCC 15 – Analog power supply (internal bias and current DAC), 5 V
VCCF 21 – Analog power supply (DACFF), 5 V
VCCL 20 – Analog power supply (L-channel I/V), 5 V
VCCR 10 – Analog power supply (R-channel I/V), 5 V
VCOM 14 – Internal bias decoupling pin
VDD 7 – Digital power supply, 3.3 V
VOUTL+ 17 O L-channel analog voltage
VOUTL– 18 O L-channel analog voltage output –
VOUTR+ 13 O R-channel analog voltage
VOUTR– 12 O R-channel analog voltage output –
ZEROL 23 O Zero flag for L-channel
ZEROR 22 O Zero flag for R-channel
(1) Schmitt-trigger input, 5-V tolerant
(2) Schmitt-trigger input and output. 5-V tolerant input. In I2C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a CMOS
output.
(3) 3-state output
(4) Schmitt-trigger input and output. 5-V tolerant input and CMOS output