DCD-F101
12
Synchronization
detection
EFM Demodulation
Slice Level
Control
CLV
Digital servo
Subcode
separation
Q CRC
Microprocessor
Interface
VCO
oscillator
Clock control
2k
´
8-bit
RAM
RAM address
generator
C1 and C2 error
detection and correction
Flag processing
Gene
ral
-purpos
e
port
s
/A
nt
i-
sh
ock
in
te
rf
ac
e
8
´
oversampling
digital filters
One-bit D/A
converter
Crystal oscillator system
Timing generator
DEFI
EFMIN
FSEQ
CLV+
CLV-
V/P
SFSY
CS
WRQ
SQOUT
CQCK
CO IN
R WC
FS
T
FO
CS
FZ
D
TO
FF
JP-
JP+
THLD
TG
L
EM
PH
EFLG
16M
4.2M
CK2
FSX
XV
SS
XOUT
XIN
XV
DD
RV
DD
MUTER
RCH
P
RCH
N
LC
HN
LC
HP
LV
SS
MUTEL
LRCKO
DFORO
DFOLO
DACKO
DOUT
ROMXA
C2F
LRSY
V
SS
V
DD
TE
ST
3
TE
ST
4
TE
ST
5
TE
ST
1
TE
ST
2
TA
I
PC
K
FR
ISET
PD
O
VV
SS
VV
DD
EF
M
O
TS
T11
PW
SBCK
SBSY
DEMO
EF
M
O
TS
T10
Level meter
Peak meter
Interpolation
and mute
Bilingual function (1)
Digital output
Bilingual function (2)
Digital
attenuator
ASDACK/P0
ASDFI N/ P1
ASDEPC/P2
ASLRCK/ P3
LV
DD
HFL
TE
S
Servo
commander
RES
LASER
CONT
RV
SS
SQOUT
CO IN
A S D E P C / P 2
A S D F I N / P 1
A S D A C K /P 0
T S T 1 0
D A C K O
D F O L O
D F O R O
L R C K O
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
RWC
WRQ
FSX
SBC
K
SFSY
PW
EFLG
SBSY
DO
UT
MU
TER
RV
DD
RC
HP
RC
HN
RV
SS
LV
SS
LCHN
LCHP
LV
DD
MU
TEL
C2F
RO
MX
A
CK2
LRSY
ASLRC
K/P
3
E M P H
T E S T 4
D E M O
J P -
J P +
V
D D
T E S T 3
T H L D
DEFI
TAI
PDO
VVS
S
ISET
VVDD
FR
VSS
EFMO
EFMO
EFMIN
TES
T
2
CLV
+
CLV
-
V/P
FOCS
FST
FZD
HFL
TES
PCK
FSE
Q
TOFF
TGL
CQCK
RES
TST11
LASER
16M
4.2M
CONT
TEST5
CS
XV
S S
XIN
XOUT
XV
D D
TEST1
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
LC78625E (IC102)
