Dell
PowerEdge M910 Technical Guide
24
Model
Speed
TDP Power
Cache
Cores QPI Speed
E7540
2.00GHz
105W
18M
6
6.4GT/s
E6540
2.00GHz
105W
18M
6
6.4GT/s
E7530
1.86GHz
105W
12M
6
5.86GT/s
E6510
1.73GHz
105W
12M
4
4.8GT/s
L7555
1.86GHz
95W
24M
8
5.86GT/s
L7545
1.86GHz
95W
18M
6
5.86GT/s
E7520
1.86GHz
95W
18M
4
4.8GT/s
6.4
Processor Configurations
The Dell™ PowerEdge™ M910 is designed to support either a dual processor configuration with
FlexMem Bridge or a four-processor configuration. In either configuration, all I/O and memory is
available in the system. While not formally supported, single processor configurations with a
processor installed in CPU1 will allow the system to boot for diagnostic purposes.
The Intel Xeon E7-2800 product family and Intel Xeon processor 6500 series are for two-socket
configurations only and
cannot
be upgraded to four-socket configurations.
6.5
FlexMem Bridge
In a four-processor configuration, the PowerEdge M910 uses only one memory controller per
processor. This single controller connects to two memory buffers via Intel SMI links. Each memory
buffer in turn connects to four DDR3 DIMMs. In a typical Intel Xeon processor 6500 or 7500 series
configuration, only the memory buffers associated with the two populated sockets would be
connected, and therefore only 16 DIMMs would be accessible.
To overcome this limitation with two processors, the M910 uses the FlexMem Bridge which allows
CPU1 and CPU2 to connect to the memory of their respective adjacent sockets (CPU3 and CPU4). The
FlexMem Bridge provides the following:
Two pass-through links for SMI
One pass-through link for QPI
The pass-through SMI links connect the two installed processors to additional SMIs, therefore the
processors will have the following memory attached:
CPU1 has access to DIMMs [A1:A8] and DIMMs [C1:C8] (those normally associated
with CPU3)
CPU2 has access to DIMMs [B1:B8] and DIMMs [D1:D8] (those normally associated
with CPU4)
The pass-through QPI link on the FlexMem Bridge provides increased performance for a 2P
configuration because it allows 2 full-bandwidth QPI links between CPU1 and CPU2 as opposed to a
single link. Figure 4 depicts the interconnection between the CPU sockets as well as connections
internal to the FlexMem Bridges. The FlexMem Bridges are only supported in sockets 3 and 4.
