Dell
PowerEdge M910 Technical Guide
22
6
Processors
6.1
Overview
The Intel
®
Xeon
®
processor E7 family and the Intel Xeon processor 6500 and 7500 series are designed
specifically for servers and workstation applications. The processors feature quad-core processing to
maximize performance and performance/watt for data center infrastructures and highly dense
deployments. These processors also feature Intel Core™ micro-architecture and Intel 64 architecture
for flexibility in 64-bit and 32-bit applications and operating systems. The Intel Xeon E7-2800, E7-
4800, and E7-8800 product family and the Intel Xeon processor 6500 and 7500 series support all
Streaming SIMD Extensions (including SSE2, SSE3, and SSE4) and Intel 64 instruction.
The Intel Xeon processor 6500 and 7500 series 4S (expandable processor) uses a 1567-pins Land Grid
Array (LGA1567) package that plugs into a surface-mount socket. The M910 provides support for two
or four processors.
Processor Cache Sizes (Package LGA1567)
Table 5.
Cache
Size
L1 cache size
32 KB instruction
(32 KB data)
L2 cache size
1.5 MB or 2 MB
L3 cache size
12 MB, 18 MB or 24 MB (shared)
6.2
Features
Key features of the Intel Xeon processor E7-2800, E7-4800, and E7-8800 product families include:
Up to ten cores per processor
Four point-to-point QuickPath Interconnect links at 6.4 GT/s
32 nm process technology
Intel HyperThreading (2 threads/core)
Up to 30 MB shared L3 cache
Intel Trusted Execution Technology (TXT) and AESNI (AES New Instructions)
RAS DDDC (Double Device Data Correct)
Key features of the Intel Xeon processor 6500 and 7500 series include:
Up to eight cores per socket
Up to 24 MB shared L3 cache
45nm process technology
Four full
‐
width, bidirectional point
‐
to
‐
point Intel QuickPath Interconnect (Intel QPI) links at
6.4 GT/s
Support for 95 W, 105 W, and 130 W processors
Four Intel Scalable Memory Interconnects (Intel SMI) at 6.4 GT/s
Socket: LS, LGA 1567 package
No termination required for non
‐
populated processors (must populate processor socket 1 first)
Integrated Intel QuickPath DDR3 memory controller
64
‐
byte cache line size
RISC/CISC hybrid architecture
Compatible with existing x86 code base
