DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 195 of 242
Field
Description of fields within Sub-Register 0x36:00 – PMSC_CTRL0
FACE
reg:36:00
bit:6
Force Accumulator Clock Enable. In normal operation this bit should be set to 0 to allow the
PMSC to control the accumulator clock as necessary for normal receiver operation. If the host
system wants to read the accumulator data, both this FACE bit and the AMCE bit (below) need
to be set to 1 to allow the accumulator reading to operate correctly.
ADCCE
reg:36:00
bit:10
(temperature and voltage) Analog-to-Digital Convertor Clock Enable. The DW1000 is equipped
with 8-bit A/D convertors to sample the IC temperature and its input battery voltage. The IC
can automatically sample the temperature and voltage as it wakes up from
. This is controlled by the ONW_RADC bit in
Sub-Register 0x2C:00 – AON_WCFG.
If
the host system wants to initiate temperature and/or voltage measurements at other times
then the clock to the Analog-to-Digital Convertor needs to be enabled via this ADCCE bit. For
more details of this functionality, please refer to section
6.4 – Measuring IC temperature and
AMCE
reg:36:00
bit:15
Accumulator Memory Clock Enable. In normal operation this bit should be set to 0 to allow
the PMSC to control the accumulator memory clock as necessary for normal receiver
operation. If the host system wants to read the accumulator data, both this AMCE bit and
FACE bit (above) need to be set to 1 to allow the accumulator reading to operate correctly.
GPCE
reg:36:00
bit:16
GPIO clock Enable. In order to use the GPIO port lines the GPCE enable must be set to 1 to
enable the clock into the GPIO block. The GPRN bit (below) must also be set to 1 to take the
GPIO port out of its reset state.
GPRN
reg:36:00
bit:17
GPIO reset (NOT), active low. In order to use the GPIO port lines GPRN bit must be set to 1 to
take the GPIO port out of its reset state. The GPCE enable bit (above) must also be set to 1 to
enable the clock into the GPIO block.
GPDCE
reg:36:00
bit:18
GPIO De-bounce Clock Enable. The DW1000 GPIO port includes a de-bounce functionality that
may be applied to input lines being used as an interrupt source. The de-bounce filter circuit
clocks the GPIO inputs into the DW1000 and removes short transients by requiring that the
input persists for two cycles of this clock before it will be seen by the interrupt handling logic.
(See
Sub-Register 0x26:24 – GPIO_IDBE
for more details). In order to use the GPIO port de-
bounce functionality this GPDCE bit must be set to 1 to enable the clock into the GPIO block.
The GPDRN bit (below) must also be set to 1 to take the GPIO port de-bounce filter circuit out
of its reset state.
This GPDCE bit also serves to enable the clock that controls the LED blink functionality and so
must be enabled in order for the LEDs to function correctly. See
for details of enabling LED functionality on GPIO lines.
Note: As this clock employs the kilohertz clock, the appropriate dividers and enables need to
be configured according to the desired functionality. See KHZCLKEN below and KHZCLKDIV in
Sub-Register 0x36:04 – PMSC_CTRL1
GPDRN
reg:36:00
bit:19
GPIO de-bounce reset (NOT), active low. In order to use the GPIO port de-bounce filter circuit
the GPDRN bit must be set to 1 to take the de-bounce filter circuit out of its reset state. The
GPDCE enable bit (above) must also be set to 1 to enable the clock into the GPIO de-bounce
circuit.
KHZCLKEN
reg:36:00
bit:23
Kilohertz clock Enable. When this bit is set to 1 it enables the divider. The divider value is set
by KHZCLKDIV in
