DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 18 of 242
State Name
State Description
the 125 MHz digital PLL clock is not running).
2.4 Power On Reset (POR)
When the external power source is applied to the DW1000 for the first time, the internal Power On Reset
(POR) circuit compares the externally applied supply voltage to an internal power-on threshold
(approximately 1.5 V), and once this threshold is passed the crystal oscillator is enabled and the external
device enable pin EXTON is asserted. An internal counter running off the low power oscillator is used to hold
the DW1000 in reset to ensure that the crystal oscillator is stable before it gets used. Once the digital reset is
de-asserted the digital core wakes up and enters the
state. From this state it will automatically turn
on the CLKPLL and wait for it to lock before entering the
Figure 9: Timing diagram and power profile for cold start POR
2.4.1 SLEEP and DEEPSLEEP
In the DW1000 very low power
state, the IC is almost completely powered down except for a
small amount of memory necessary to maintain IC configurations. This is the lowest power mode of the IC
where the power drain is < 100 nA. To wake the IC from
requires an external agent to assert the
WAKEUP input line or the external host microprocessor to initiate an SPI transaction to assert the SPICSn
input.
The DW1000 also includes a low power
state where the IC can wake itself from sleeping as a result of
the elapsing of a sleep timer that is running from a low-powered ring oscillator internal to the DW1000 IC.
In this
state the power drain is < 1 µA. The DW1000 may wake from
elapses. The WAKEUP or SPICSn inputs may also be used to wake the device.
IDLE
INIT
OFF
WAKEUP
CLKPLL locked
Crystal stable,
RSTn=1
POWERON
VDDBATT
EXTON
XTAL
VDDDIG
RSTn
V
por
SPI comms
up to 3MHz
SPI comms up
to max SPI frequency
Battery Inserted
VDDBATT switched on
300µs
4ms
5µs
7µs
CLKPLL
Lock
CLKPLL
enabled
SPI comms not advised
as PLL locks
